/* Copyright (c) 2025 Beijing Semidrive Technology Corporation
 * SPDX-License-Identifier: Apache-2.0
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
 * you may not use this file except in compliance with the License.
 * You may obtain a copy of the License at
 *
 * http://www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an "AS IS" BASIS,
 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 * See the License for the specific language governing permissions and
 * limitations under the License.
 */
/** *****************************************************************************************************
 *  \file     Port_pinmap.h                                                                              *
 *  \brief    his file contains data structures header for PORT MCAL driver.                            *
 *                                                                                                      *
 * <table>                                                                                              *
 * <tr><th>Date           <th>Version                                                                   *
 * <tr><td>2023/07/14     <td>1.0.0                                                                     *
 * </table>                                                                                             *
 *******************************************************************************************************/

#ifndef PORT_PINMAP_H
#define PORT_PINMAP_H
#ifdef __cplusplus
extern "C" {
#endif

/********************************************************************************************************
 *                                      Include header files                                            *
 *******************************************************************************************************/
#include "Port_Types.h"
/********************************************************************************************************
 *                                 Global Macro definition                                              *
 *******************************************************************************************************/
/* PORT REGISTER BASE ADDRESS*/
#define  PORT_IOMUXC_TOP_BASE          (0xF8100000ul)
#define  PORT_IOMUXC_RTC_BASE          (0xF0070000ul)
#define  PORT_IOMUXC_LP_BASE           (0xF07A0000ul)
#define  PORT_IOMUXC_CPU_BASE          (0xF85F0000ul)
#define  PORT_IOMUXC_MAIN_DOWN_BASE    (0xF9040000ul)
#define  PORT_IOMUXC_MAIN_UP_BASE      (0xF9050000ul)

#define  PORT_GPIO_SF1_BASE            (0xF81E0000ul)
#define  PORT_GPIO_SF2_BASE            (0xF81F0000ul)
#define  PORT_GPIO_LP_BASE             (0xF04B0000ul)


/** \brief port pin total number*/
#define PORT_PIN_NUM                    (394U)

/** \brief port pin input select number*/
#define PORT_INPUT_SELECT_NUM           (998U)


/** \brief cpu port pin group number*/
#define PORT_CPU_PIN_GROUP_NUM          (2U)

/** \brief cpu domain port pin start index*/
#define PORT_CPU_PIN_START              (96U)
/** \brief cpu domain port pin number*/
#define PORT_CPU_PIN_NUM                (32U)

/** \brief cpu domain port pin start index of group2*/
#define PORT_CPU_PIN_START2             (160U)
/** \brief cpu domain port pin number of group2*/
#define PORT_CPU_PIN_NUM2               (32U)


/** \brief lp port pin group number*/
#define PORT_LP_PIN_GROUP_NUM           (1U)

/** \brief lp domain port pin start index*/
#define PORT_LP_PIN_START               (312U)
/** \brief lp domain port pin number*/
#define PORT_LP_PIN_NUM                 (79U)


/** \brief main down port pin group number*/
#define PORT_MAIN_DOWN_PIN_GROUP_NUM    (1U)

/** \brief main down domain port pin start index*/
#define PORT_MAIN_DOWN_PIN_START        (224U)
/** \brief main down domain port pin number*/
#define PORT_MAIN_DOWN_PIN_NUM          (48U)


/** \brief main up port pin group number*/
#define PORT_MAIN_UP_PIN_GROUP_NUM       (3U)

/** \brief main up domain port pin start index*/
#define PORT_MAIN_UP_PIN_START           (192U)
/** \brief main up domain port pin number*/
#define PORT_MAIN_UP_PIN_NUM             (32U)

/** \brief main up domain port pin start index of group2*/
#define PORT_MAIN_UP_PIN_START2           (128U)
/** \brief main up domain port pin number of group2*/
#define PORT_MAIN_UP_PIN_NUM2             (32U)

/** \brief main up domain port pin start index of group3*/
#define PORT_MAIN_UP_PIN_START3           (272U)
/** \brief main up domain port pin number of group3*/
#define PORT_MAIN_UP_PIN_NUM3             (16U)


/** \brief rtc port pin group number*/
#define PORT_RTC_PIN_GROUP_NUM          (3U)

/** \brief rtc domain port pin start index*/
#define PORT_RTC_PIN_START              (288U)
/** \brief rtc domain port pin number*/
#define PORT_RTC_PIN_NUM                (2U)

/** \brief rtc domain port pin start index of group2*/
#define PORT_RTC_PIN_START2             (391U)
/** \brief rtc domain port pin number of group2*/
#define PORT_RTC_PIN_NUM2               (1U)

/** \brief rtc domain port pin start index of group3*/
#define PORT_RTC_PIN_START3             (290U)
/** \brief rtc domain port pin number of group3*/
#define PORT_RTC_PIN_NUM3               (20U)


/** \brief top port pin group number*/
#define PORT_TOP_PIN_GROUP_NUM          (1U)

/** \brief rtc domain port pin start index*/
#define PORT_TOP_PIN_START              (0U)
/** \brief rtc domain port pin number*/
#define PORT_TOP_PIN_NUM                (96U)


#define GPIO_K0            0U
#define GPIO_K1            1U
#define GPIO_K2            2U
#define GPIO_K3            3U
#define GPIO_K4            4U
#define GPIO_K5            5U
#define GPIO_K6            6U
#define GPIO_K7            7U
#define GPIO_K8            8U
#define GPIO_K9            9U
#define GPIO_K10           10U
#define GPIO_K11           11U
#define GPIO_K12           12U
#define GPIO_K13           13U
#define GPIO_K14           14U
#define GPIO_K15           15U
#define GPIO_K16           16U
#define GPIO_K17           17U
#define GPIO_K18           18U
#define GPIO_K19           19U
#define GPIO_K20           20U
#define GPIO_K21           21U
#define GPIO_K22           22U
#define GPIO_K23           23U
#define GPIO_U0            24U
#define GPIO_U1            25U
#define GPIO_U2            26U
#define GPIO_U3            27U
#define GPIO_U4            28U
#define GPIO_U5            29U
#define GPIO_U6            30U
#define GPIO_U7            31U
#define GPIO_U8            32U
#define GPIO_U9            33U
#define GPIO_U10           34U
#define GPIO_U11           35U
#define GPIO_U12           36U
#define GPIO_U13           37U
#define GPIO_U14           38U
#define GPIO_U15           39U
#define GPIO_U16           40U
#define GPIO_U17           41U
#define GPIO_U18           42U
#define GPIO_U19           43U
#define GPIO_U20           44U
#define GPIO_U21           45U
#define GPIO_U22           46U
#define GPIO_U23           47U
#define GPIO_A0            48U
#define GPIO_A1            49U
#define GPIO_A2            50U
#define GPIO_A3            51U
#define GPIO_A4            52U
#define GPIO_A5            53U
#define GPIO_A6            54U
#define GPIO_A7            55U
#define GPIO_A8            56U
#define GPIO_A9            57U
#define GPIO_A10           58U
#define GPIO_A11           59U
#define GPIO_A12           60U
#define GPIO_A13           61U
#define GPIO_A14           62U
#define GPIO_A15           63U
#define GPIO_B0            64U
#define GPIO_B1            65U
#define GPIO_B2            66U
#define GPIO_B3            67U
#define GPIO_B4            68U
#define GPIO_B5            69U
#define GPIO_B6            70U
#define GPIO_B7            71U
#define GPIO_B8            72U
#define GPIO_B9            73U
#define GPIO_B10           74U
#define GPIO_B11           75U
#define GPIO_B12           76U
#define GPIO_B13           77U
#define GPIO_B14           78U
#define GPIO_B15           79U
#define GPIO_C0            80U
#define GPIO_C1            81U
#define GPIO_C2            82U
#define GPIO_C3            83U
#define GPIO_C4            84U
#define GPIO_C5            85U
#define GPIO_C6            86U
#define GPIO_C7            87U
#define GPIO_C8            88U
#define GPIO_C9            89U
#define GPIO_C10           90U
#define GPIO_C11           91U
#define GPIO_C12           92U
#define GPIO_C13           93U
#define GPIO_C14           94U
#define GPIO_C15           95U
#define GPIO_E0            96U
#define GPIO_E1            97U
#define GPIO_E2            98U
#define GPIO_E3            99U
#define GPIO_E4            100U
#define GPIO_E5            101U
#define GPIO_E6            102U
#define GPIO_E7            103U
#define GPIO_E8            104U
#define GPIO_E9            105U
#define GPIO_E10           106U
#define GPIO_E11           107U
#define GPIO_E12           108U
#define GPIO_E13           109U
#define GPIO_E14           110U
#define GPIO_E15           111U
#define GPIO_E16           112U
#define GPIO_E17           113U
#define GPIO_E18           114U
#define GPIO_E19           115U
#define GPIO_E20           116U
#define GPIO_E21           117U
#define GPIO_E22           118U
#define GPIO_E23           119U
#define GPIO_E24           120U
#define GPIO_E25           121U
#define GPIO_E26           122U
#define GPIO_E27           123U
#define GPIO_E28           124U
#define GPIO_E29           125U
#define GPIO_E30           126U
#define GPIO_E31           127U
#define GPIO_S0            128U
#define GPIO_S1            129U
#define GPIO_S2            130U
#define GPIO_S3            131U
#define GPIO_S4            132U
#define GPIO_S5            133U
#define GPIO_S6            134U
#define GPIO_S7            135U
#define GPIO_S8            136U
#define GPIO_S9            137U
#define GPIO_S10           138U
#define GPIO_S11           139U
#define GPIO_S12           140U
#define GPIO_S13           141U
#define GPIO_S14           142U
#define GPIO_S15           143U
#define GPIO_S16           144U
#define GPIO_S17           145U
#define GPIO_S18           146U
#define GPIO_S19           147U
#define GPIO_S20           148U
#define GPIO_S21           149U
#define GPIO_S22           150U
#define GPIO_S23           151U
#define GPIO_S24           152U
#define GPIO_S25           153U
#define GPIO_S26           154U
#define GPIO_S27           155U
#define GPIO_S28           156U
#define GPIO_S29           157U
#define GPIO_S30           158U
#define GPIO_S31           159U
#define GPIO_M0            160U
#define GPIO_M1            161U
#define GPIO_M2            162U
#define GPIO_M3            163U
#define GPIO_M4            164U
#define GPIO_M5            165U
#define GPIO_M6            166U
#define GPIO_M7            167U
#define GPIO_M8            168U
#define GPIO_M9            169U
#define GPIO_M10           170U
#define GPIO_M11           171U
#define GPIO_M12           172U
#define GPIO_M13           173U
#define GPIO_M14           174U
#define GPIO_M15           175U
#define GPIO_M16           176U
#define GPIO_M17           177U
#define GPIO_M18           178U
#define GPIO_M19           179U
#define GPIO_M20           180U
#define GPIO_M21           181U
#define GPIO_M22           182U
#define GPIO_M23           183U
#define GPIO_M24           184U
#define GPIO_M25           185U
#define GPIO_M26           186U
#define GPIO_M27           187U
#define GPIO_M28           188U
#define GPIO_M29           189U
#define GPIO_M30           190U
#define GPIO_M31           191U
#define GPIO_X0            192U
#define GPIO_X1            193U
#define GPIO_X2            194U
#define GPIO_X3            195U
#define GPIO_X4            196U
#define GPIO_X5            197U
#define GPIO_X6            198U
#define GPIO_X7            199U
#define GPIO_X8            200U
#define GPIO_X9            201U
#define GPIO_X10           202U
#define GPIO_X11           203U
#define GPIO_X12           204U
#define GPIO_X13           205U
#define GPIO_X14           206U
#define GPIO_X15           207U
#define GPIO_Y0            208U
#define GPIO_Y1            209U
#define GPIO_Y2            210U
#define GPIO_Y3            211U
#define GPIO_Y4            212U
#define GPIO_Y5            213U
#define GPIO_Y6            214U
#define GPIO_Y7            215U
#define GPIO_Y8            216U
#define GPIO_Y9            217U
#define GPIO_Y10           218U
#define GPIO_Y11           219U
#define GPIO_Y12           220U
#define GPIO_Y13           221U
#define GPIO_Y14           222U
#define GPIO_Y15           223U
#define GPIO_H0            224U
#define GPIO_H1            225U
#define GPIO_H2            226U
#define GPIO_H3            227U
#define GPIO_H4            228U
#define GPIO_H5            229U
#define GPIO_H6            230U
#define GPIO_H7            231U
#define GPIO_H8            232U
#define GPIO_H9            233U
#define GPIO_H10           234U
#define GPIO_H11           235U
#define GPIO_H12           236U
#define GPIO_H13           237U
#define GPIO_H14           238U
#define GPIO_H15           239U
#define GPIO_G0            240U
#define GPIO_G1            241U
#define GPIO_G2            242U
#define GPIO_G3            243U
#define GPIO_G4            244U
#define GPIO_G5            245U
#define GPIO_G6            246U
#define GPIO_G7            247U
#define GPIO_G8            248U
#define GPIO_G9            249U
#define GPIO_G10           250U
#define GPIO_G11           251U
#define GPIO_G12           252U
#define GPIO_G13           253U
#define GPIO_G14           254U
#define GPIO_G15           255U
#define GPIO_G16           256U
#define GPIO_G17           257U
#define GPIO_G18           258U
#define GPIO_G19           259U
#define GPIO_G20           260U
#define GPIO_G21           261U
#define GPIO_G22           262U
#define GPIO_G23           263U
#define GPIO_G24           264U
#define GPIO_G25           265U
#define GPIO_G26           266U
#define GPIO_G27           267U
#define GPIO_G28           268U
#define GPIO_G29           269U
#define GPIO_G30           270U
#define GPIO_G31           271U
#define GPIO_F0            272U
#define GPIO_F1            273U
#define GPIO_F2            274U
#define GPIO_F3            275U
#define GPIO_F4            276U
#define GPIO_F5            277U
#define GPIO_F6            278U
#define GPIO_F7            279U
#define GPIO_F8            280U
#define GPIO_F9            281U
#define GPIO_F10           282U
#define GPIO_F11           283U
#define GPIO_F12           284U
#define GPIO_F13           285U
#define GPIO_F14           286U
#define GPIO_F15           287U
#define SYS_MODE0          288U
#define SYS_MODE1          289U
#define SYS_BUTTON         290U
#define SYS_CTRL0          291U
#define SYS_CTRL1          292U
#define SYS_GPIO0          293U
#define SYS_GPIO1          294U
#define SYS_GPIO2          295U
#define SYS_GPIO3          296U
#define SYS_GPIO4          297U
#define SYS_GPIO5          298U
#define SYS_GPIO6          299U
#define SYS_GPIO7          300U
#define SYS_GPIO8          301U
#define SYS_GPIO9          302U
#define SYS_GPIO10         303U
#define SYS_GPIO11         304U
#define SYS_GPIO12         305U
#define SYS_GPIO13         306U
#define SYS_GPIO14         307U
#define SYS_GPIO15         308U
#define SYS_GPIO16         309U
#define XTALI_32K          310U
#define XTALI_24M          311U
#define SEM_FAULT0         312U
#define SEM_FAULT1         313U
#define JTAG_TDI           314U
#define JTAG_TDO           315U
#define JTAG_TRST_N        316U
#define JTAG_TMS           317U
#define JTAG_TCK           318U
#define GPIO_J0            319U
#define GPIO_J1            320U
#define GPIO_J2            321U
#define GPIO_J3            322U
#define GPIO_J4            323U
#define GPIO_J5            324U
#define GPIO_J6            325U
#define GPIO_J7            326U
#define GPIO_LA0           327U
#define GPIO_LA1           328U
#define GPIO_LA2           329U
#define GPIO_LA3           330U
#define GPIO_LA4           331U
#define GPIO_LA5           332U
#define GPIO_LA6           333U
#define GPIO_LA7           334U
#define GPIO_LA8           335U
#define GPIO_LA9           336U
#define GPIO_LA10          337U
#define GPIO_LA11          338U
#define GPIO_LA12          339U
#define GPIO_LA13          340U
#define GPIO_LA14          341U
#define GPIO_LA15          342U
#define GPIO_LA16          343U
#define GPIO_LA17          344U
#define GPIO_LA18          345U
#define GPIO_LA19          346U
#define GPIO_LA20          347U
#define GPIO_LA21          348U
#define GPIO_LA22          349U
#define GPIO_LA23          350U
#define GPIO_LA24          351U
#define GPIO_LA25          352U
#define GPIO_LA26          353U
#define GPIO_LA27          354U
#define GPIO_LA28          355U
#define GPIO_LA29          356U
#define GPIO_LA30          357U
#define GPIO_LA31          358U
#define GPIO_LD0           359U
#define GPIO_LD1           360U
#define GPIO_LD2           361U
#define GPIO_LD3           362U
#define GPIO_LD4           363U
#define GPIO_LD5           364U
#define GPIO_LD6           365U
#define GPIO_LD7           366U
#define GPIO_LD8           367U
#define GPIO_LD9           368U
#define GPIO_LD10          369U
#define GPIO_LD11          370U
#define GPIO_LD12          371U
#define GPIO_LD13          372U
#define GPIO_LD14          373U
#define GPIO_LD15          374U
#define GPIO_LD16          375U
#define GPIO_LD17          376U
#define GPIO_LD18          377U
#define GPIO_LD19          378U
#define GPIO_LD20          379U
#define GPIO_LD21          380U
#define GPIO_LD22          381U
#define GPIO_LD23          382U
#define GPIO_LD24          383U
#define GPIO_LD25          384U
#define GPIO_LD26          385U
#define GPIO_LD27          386U
#define GPIO_LD28          387U
#define GPIO_LD29          388U
#define GPIO_LD30          389U
#define GPIO_LD31          390U
#define SYS_POR_B          391U
#define XTALO_32K          392U
#define XTALO_24M          393U

/********************************************************************************************************
 *                                  Private Variable Definitions                                        *
 *******************************************************************************************************/
#define PORT_START_SEC_CONST_UNSPECIFIED
#include "Port_MemMap.h"

/** \brief  input select table */
/*PRQA S 1533 3*/
static const Port_InputSelectType Port_PinctrlIs[PORT_INPUT_SELECT_NUM] = {
    {     GPIO_K0,    4,    PORT_IOMUXC_TOP_BASE,    0x3080U,   0},
    {     GPIO_K0,    5,    PORT_IOMUXC_TOP_BASE,    0x3084U,   0},
    {     GPIO_K1,    4,    PORT_IOMUXC_TOP_BASE,    0x3008U,   1},
    {     GPIO_K1,    5,    PORT_IOMUXC_TOP_BASE,    0x3088U,   0},
    {     GPIO_K2,    2,    PORT_IOMUXC_TOP_BASE,    0x3030U,   1},
    {     GPIO_K2,    4,    PORT_IOMUXC_TOP_BASE,    0x308cU,   0},
    {     GPIO_K2,    5,    PORT_IOMUXC_TOP_BASE,    0x3090U,   0},
    {     GPIO_K3,    4,    PORT_IOMUXC_TOP_BASE,    0x3094U,   0},
    {     GPIO_K3,    5,    PORT_IOMUXC_TOP_BASE,    0x3098U,   0},
    {     GPIO_K4,    2,    PORT_IOMUXC_TOP_BASE,    0x3034U,   1},
    {     GPIO_K4,    4,    PORT_IOMUXC_TOP_BASE,    0x309cU,   0},
    {     GPIO_K4,    5,    PORT_IOMUXC_TOP_BASE,    0x30a0U,   0},
    {     GPIO_K5,    4,    PORT_IOMUXC_TOP_BASE,    0x30a4U,   0},
    {     GPIO_K5,    5,    PORT_IOMUXC_TOP_BASE,    0x30a8U,   0},
    {     GPIO_K6,    3,    PORT_IOMUXC_TOP_BASE,    0x30acU,   0},
    {     GPIO_K6,    4,    PORT_IOMUXC_TOP_BASE,    0x30b0U,   0},
    {     GPIO_K6,    5,    PORT_IOMUXC_TOP_BASE,    0x30b4U,   0},
    {     GPIO_K7,    3,    PORT_IOMUXC_TOP_BASE,    0x30b8U,   0},
    {     GPIO_K7,    4,    PORT_IOMUXC_TOP_BASE,    0x300cU,   1},
    {     GPIO_K7,    5,    PORT_IOMUXC_TOP_BASE,    0x30bcU,   0},
    {     GPIO_K8,    3,    PORT_IOMUXC_TOP_BASE,    0x30c0U,   0},
    {     GPIO_K8,    4,    PORT_IOMUXC_TOP_BASE,    0x30c4U,   0},
    {     GPIO_K8,    5,    PORT_IOMUXC_TOP_BASE,    0x30c8U,   0},
    {     GPIO_K9,    3,    PORT_IOMUXC_TOP_BASE,    0x30ccU,   0},
    {     GPIO_K9,    4,    PORT_IOMUXC_TOP_BASE,    0x3010U,   1},
    {     GPIO_K9,    5,    PORT_IOMUXC_TOP_BASE,    0x30d0U,   0},
    {    GPIO_K10,    2,    PORT_IOMUXC_TOP_BASE,    0x3038U,   1},
    {    GPIO_K10,    3,    PORT_IOMUXC_TOP_BASE,    0x30d4U,   0},
    {    GPIO_K10,    4,    PORT_IOMUXC_TOP_BASE,    0x30d8U,   0},
    {    GPIO_K10,    5,    PORT_IOMUXC_TOP_BASE,    0x30dcU,   0},
    {    GPIO_K11,    3,    PORT_IOMUXC_TOP_BASE,    0x30e0U,   0},
    {    GPIO_K11,    4,    PORT_IOMUXC_TOP_BASE,    0x30e4U,   0},
    {    GPIO_K11,    5,    PORT_IOMUXC_TOP_BASE,    0x30e8U,   0},
    {    GPIO_K12,    2,    PORT_IOMUXC_TOP_BASE,    0x303cU,   1},
    {    GPIO_K12,    3,    PORT_IOMUXC_TOP_BASE,    0x30ecU,   0},
    {    GPIO_K12,    4,    PORT_IOMUXC_TOP_BASE,    0x30f0U,   0},
    {    GPIO_K12,    5,    PORT_IOMUXC_TOP_BASE,    0x30f4U,   0},
    {    GPIO_K13,    3,    PORT_IOMUXC_TOP_BASE,    0x30f8U,   0},
    {    GPIO_K13,    4,    PORT_IOMUXC_TOP_BASE,    0x30fcU,   0},
    {    GPIO_K13,    5,    PORT_IOMUXC_TOP_BASE,    0x3100U,   0},
    {    GPIO_K14,    1,    PORT_IOMUXC_TOP_BASE,    0x3104U,   0},
    {    GPIO_K14,    2,    PORT_IOMUXC_TOP_BASE,    0x3040U,   1},
    {    GPIO_K14,    3,    PORT_IOMUXC_TOP_BASE,    0x3108U,   0},
    {    GPIO_K14,    4,    PORT_IOMUXC_TOP_BASE,    0x310cU,   0},
    {    GPIO_K14,    5,    PORT_IOMUXC_TOP_BASE,    0x3110U,   0},
    {    GPIO_K15,    1,    PORT_IOMUXC_TOP_BASE,    0x3114U,   0},
    {    GPIO_K15,    3,    PORT_IOMUXC_TOP_BASE,    0x3118U,   0},
    {    GPIO_K15,    4,    PORT_IOMUXC_TOP_BASE,    0x3014U,   1},
    {    GPIO_K15,    5,    PORT_IOMUXC_TOP_BASE,    0x311cU,   0},
    {    GPIO_K16,    1,    PORT_IOMUXC_TOP_BASE,    0x3120U,   0},
    {    GPIO_K16,    2,    PORT_IOMUXC_TOP_BASE,    0x3044U,   1},
    {    GPIO_K16,    3,    PORT_IOMUXC_TOP_BASE,    0x3124U,   0},
    {    GPIO_K16,    4,    PORT_IOMUXC_TOP_BASE,    0x3128U,   0},
    {    GPIO_K16,    5,    PORT_IOMUXC_TOP_BASE,    0x312cU,   0},
    {    GPIO_K17,    1,    PORT_IOMUXC_TOP_BASE,    0x3130U,   0},
    {    GPIO_K17,    3,    PORT_IOMUXC_TOP_BASE,    0x3134U,   0},
    {    GPIO_K17,    4,    PORT_IOMUXC_TOP_BASE,    0x3018U,   1},
    {    GPIO_K17,    5,    PORT_IOMUXC_TOP_BASE,    0x3138U,   0},
    {    GPIO_K18,    1,    PORT_IOMUXC_TOP_BASE,    0x313cU,   0},
    {    GPIO_K18,    3,    PORT_IOMUXC_TOP_BASE,    0x3140U,   0},
    {    GPIO_K18,    4,    PORT_IOMUXC_TOP_BASE,    0x3144U,   0},
    {    GPIO_K18,    5,    PORT_IOMUXC_TOP_BASE,    0x3148U,   0},
    {    GPIO_K19,    1,    PORT_IOMUXC_TOP_BASE,    0x314cU,   0},
    {    GPIO_K19,    3,    PORT_IOMUXC_TOP_BASE,    0x3150U,   0},
    {    GPIO_K19,    4,    PORT_IOMUXC_TOP_BASE,    0x3154U,   0},
    {    GPIO_K19,    5,    PORT_IOMUXC_TOP_BASE,    0x3158U,   0},
    {    GPIO_K20,    3,    PORT_IOMUXC_TOP_BASE,    0x315cU,   0},
    {    GPIO_K20,    4,    PORT_IOMUXC_TOP_BASE,    0x3160U,   0},
    {    GPIO_K20,    5,    PORT_IOMUXC_TOP_BASE,    0x3164U,   0},
    {    GPIO_K21,    3,    PORT_IOMUXC_TOP_BASE,    0x3168U,   0},
    {    GPIO_K21,    4,    PORT_IOMUXC_TOP_BASE,    0x316cU,   0},
    {    GPIO_K21,    5,    PORT_IOMUXC_TOP_BASE,    0x3170U,   0},
    {    GPIO_K22,    3,    PORT_IOMUXC_TOP_BASE,    0x3174U,   0},
    {    GPIO_K22,    4,    PORT_IOMUXC_TOP_BASE,    0x3178U,   0},
    {    GPIO_K22,    5,    PORT_IOMUXC_TOP_BASE,    0x317cU,   0},
    {    GPIO_K23,    3,    PORT_IOMUXC_TOP_BASE,    0x3180U,   0},
    {    GPIO_K23,    4,    PORT_IOMUXC_TOP_BASE,    0x301cU,   1},
    {    GPIO_K23,    5,    PORT_IOMUXC_TOP_BASE,    0x3184U,   0},
    {     GPIO_U0,    3,    PORT_IOMUXC_TOP_BASE,    0x3188U,   0},
    {     GPIO_U0,    4,    PORT_IOMUXC_TOP_BASE,    0x318cU,   0},
    {     GPIO_U0,    5,    PORT_IOMUXC_TOP_BASE,    0x3190U,   0},
    {     GPIO_U1,    3,    PORT_IOMUXC_TOP_BASE,    0x3194U,   0},
    {     GPIO_U1,    4,    PORT_IOMUXC_TOP_BASE,    0x3020U,   1},
    {     GPIO_U1,    5,    PORT_IOMUXC_TOP_BASE,    0x3198U,   0},
    {     GPIO_U2,    2,    PORT_IOMUXC_TOP_BASE,    0x3048U,   1},
    {     GPIO_U2,    3,    PORT_IOMUXC_TOP_BASE,    0x319cU,   0},
    {     GPIO_U2,    4,    PORT_IOMUXC_TOP_BASE,    0x31a0U,   0},
    {     GPIO_U2,    5,    PORT_IOMUXC_TOP_BASE,    0x31a4U,   0},
    {     GPIO_U3,    3,    PORT_IOMUXC_TOP_BASE,    0x31a8U,   0},
    {     GPIO_U3,    4,    PORT_IOMUXC_TOP_BASE,    0x31acU,   0},
    {     GPIO_U3,    5,    PORT_IOMUXC_TOP_BASE,    0x31b0U,   0},
    {     GPIO_U4,    2,    PORT_IOMUXC_TOP_BASE,    0x304cU,   1},
    {     GPIO_U4,    3,    PORT_IOMUXC_TOP_BASE,    0x31b4U,   0},
    {     GPIO_U4,    4,    PORT_IOMUXC_TOP_BASE,    0x31b8U,   0},
    {     GPIO_U4,    5,    PORT_IOMUXC_TOP_BASE,    0x31bcU,   0},
    {     GPIO_U5,    3,    PORT_IOMUXC_TOP_BASE,    0x31c0U,   0},
    {     GPIO_U5,    4,    PORT_IOMUXC_TOP_BASE,    0x31c4U,   0},
    {     GPIO_U5,    5,    PORT_IOMUXC_TOP_BASE,    0x31c8U,   0},
    {     GPIO_U6,    3,    PORT_IOMUXC_TOP_BASE,    0x31ccU,   0},
    {     GPIO_U6,    4,    PORT_IOMUXC_TOP_BASE,    0x31d0U,   0},
    {     GPIO_U6,    5,    PORT_IOMUXC_TOP_BASE,    0x31d4U,   0},
    {     GPIO_U7,    4,    PORT_IOMUXC_TOP_BASE,    0x3024U,   1},
    {     GPIO_U7,    5,    PORT_IOMUXC_TOP_BASE,    0x31d8U,   0},
    {     GPIO_U8,    2,    PORT_IOMUXC_TOP_BASE,    0x3038U,   2},
    {     GPIO_U8,    5,    PORT_IOMUXC_TOP_BASE,    0x31dcU,   0},
    {     GPIO_U9,    5,    PORT_IOMUXC_TOP_BASE,    0x31e0U,   0},
    {    GPIO_U10,    2,    PORT_IOMUXC_TOP_BASE,    0x303cU,   2},
    {    GPIO_U10,    5,    PORT_IOMUXC_TOP_BASE,    0x312cU,   1},
    {    GPIO_U11,    5,    PORT_IOMUXC_TOP_BASE,    0x3138U,   1},
    {    GPIO_U12,    3,    PORT_IOMUXC_TOP_BASE,    0x31e4U,   0},
    {    GPIO_U12,    5,    PORT_IOMUXC_TOP_BASE,    0x31e8U,   0},
    {    GPIO_U13,    3,    PORT_IOMUXC_TOP_BASE,    0x31ecU,   0},
    {    GPIO_U13,    5,    PORT_IOMUXC_TOP_BASE,    0x31f0U,   0},
    {    GPIO_U14,    3,    PORT_IOMUXC_TOP_BASE,    0x31f4U,   0},
    {    GPIO_U14,    5,    PORT_IOMUXC_TOP_BASE,    0x31f8U,   0},
    {    GPIO_U15,    3,    PORT_IOMUXC_TOP_BASE,    0x31fcU,   0},
    {    GPIO_U15,    5,    PORT_IOMUXC_TOP_BASE,    0x3200U,   0},
    {    GPIO_U16,    3,    PORT_IOMUXC_TOP_BASE,    0x3204U,   0},
    {    GPIO_U16,    5,    PORT_IOMUXC_TOP_BASE,    0x3208U,   0},
    {    GPIO_U17,    3,    PORT_IOMUXC_TOP_BASE,    0x320cU,   0},
    {    GPIO_U17,    5,    PORT_IOMUXC_TOP_BASE,    0x3210U,   0},
    {    GPIO_U18,    3,    PORT_IOMUXC_TOP_BASE,    0x3214U,   0},
    {    GPIO_U18,    5,    PORT_IOMUXC_TOP_BASE,    0x3218U,   0},
    {    GPIO_U19,    5,    PORT_IOMUXC_TOP_BASE,    0x321cU,   0},
    {    GPIO_U20,    5,    PORT_IOMUXC_TOP_BASE,    0x3220U,   0},
    {    GPIO_U21,    5,    PORT_IOMUXC_TOP_BASE,    0x3224U,   0},
    {    GPIO_U22,    5,    PORT_IOMUXC_TOP_BASE,    0x3228U,   0},
    {    GPIO_U23,    5,    PORT_IOMUXC_TOP_BASE,    0x322cU,   0},
    {     GPIO_A0,    4,    PORT_IOMUXC_TOP_BASE,    0x3230U,   0},
    {     GPIO_A0,    5,    PORT_IOMUXC_TOP_BASE,    0x3148U,   1},
    {     GPIO_A0,    6,    PORT_IOMUXC_TOP_BASE,    0x3234U,   0},
    {     GPIO_A1,    4,    PORT_IOMUXC_TOP_BASE,    0x3028U,   1},
    {     GPIO_A1,    5,    PORT_IOMUXC_TOP_BASE,    0x3158U,   1},
    {     GPIO_A1,    6,    PORT_IOMUXC_TOP_BASE,    0x3238U,   0},
    {     GPIO_A2,    1,    PORT_IOMUXC_TOP_BASE,    0x323cU,   0},
    {     GPIO_A2,    3,    PORT_IOMUXC_TOP_BASE,    0x3240U,   0},
    {     GPIO_A2,    4,    PORT_IOMUXC_TOP_BASE,    0x3244U,   0},
    {     GPIO_A2,    5,    PORT_IOMUXC_TOP_BASE,    0x3164U,   1},
    {     GPIO_A2,    6,    PORT_IOMUXC_TOP_BASE,    0x323cU,   1},
    {     GPIO_A3,    1,    PORT_IOMUXC_TOP_BASE,    0x3248U,   0},
    {     GPIO_A3,    3,    PORT_IOMUXC_TOP_BASE,    0x324cU,   0},
    {     GPIO_A3,    4,    PORT_IOMUXC_TOP_BASE,    0x3250U,   0},
    {     GPIO_A3,    5,    PORT_IOMUXC_TOP_BASE,    0x3170U,   1},
    {     GPIO_A3,    6,    PORT_IOMUXC_TOP_BASE,    0x3248U,   1},
    {     GPIO_A4,    1,    PORT_IOMUXC_TOP_BASE,    0x3234U,   1},
    {     GPIO_A4,    3,    PORT_IOMUXC_TOP_BASE,    0x3254U,   0},
    {     GPIO_A4,    4,    PORT_IOMUXC_TOP_BASE,    0x3258U,   0},
    {     GPIO_A4,    5,    PORT_IOMUXC_TOP_BASE,    0x317cU,   1},
    {     GPIO_A4,    6,    PORT_IOMUXC_TOP_BASE,    0x325cU,   0},
    {     GPIO_A5,    1,    PORT_IOMUXC_TOP_BASE,    0x3238U,   1},
    {     GPIO_A5,    3,    PORT_IOMUXC_TOP_BASE,    0x3260U,   0},
    {     GPIO_A5,    4,    PORT_IOMUXC_TOP_BASE,    0x3264U,   0},
    {     GPIO_A5,    5,    PORT_IOMUXC_TOP_BASE,    0x3184U,   1},
    {     GPIO_A5,    6,    PORT_IOMUXC_TOP_BASE,    0x3268U,   0},
    {     GPIO_A6,    2,    PORT_IOMUXC_TOP_BASE,    0x3050U,   1},
    {     GPIO_A6,    3,    PORT_IOMUXC_TOP_BASE,    0x326cU,   0},
    {     GPIO_A6,    4,    PORT_IOMUXC_TOP_BASE,    0x3270U,   0},
    {     GPIO_A6,    5,    PORT_IOMUXC_TOP_BASE,    0x31e8U,   1},
    {     GPIO_A7,    3,    PORT_IOMUXC_TOP_BASE,    0x3274U,   0},
    {     GPIO_A7,    4,    PORT_IOMUXC_TOP_BASE,    0x302cU,   1},
    {     GPIO_A7,    5,    PORT_IOMUXC_TOP_BASE,    0x31f0U,   1},
    {     GPIO_A8,    2,    PORT_IOMUXC_TOP_BASE,    0x3054U,   1},
    {     GPIO_A8,    3,    PORT_IOMUXC_TOP_BASE,    0x3278U,   0},
    {     GPIO_A8,    5,    PORT_IOMUXC_TOP_BASE,    0x31f8U,   1},
    {     GPIO_A8,    6,    PORT_IOMUXC_TOP_BASE,    0x327cU,   0},
    {     GPIO_A9,    1,    PORT_IOMUXC_TOP_BASE,    0x3280U,   0},
    {     GPIO_A9,    3,    PORT_IOMUXC_TOP_BASE,    0x30b8U,   1},
    {     GPIO_A9,    5,    PORT_IOMUXC_TOP_BASE,    0x3200U,   1},
    {     GPIO_A9,    6,    PORT_IOMUXC_TOP_BASE,    0x3284U,   0},
    {    GPIO_A10,    3,    PORT_IOMUXC_TOP_BASE,    0x30c0U,   1},
    {    GPIO_A10,    4,    PORT_IOMUXC_TOP_BASE,    0x3288U,   0},
    {    GPIO_A10,    5,    PORT_IOMUXC_TOP_BASE,    0x3208U,   1},
    {    GPIO_A11,    1,    PORT_IOMUXC_TOP_BASE,    0x328cU,   0},
    {    GPIO_A11,    3,    PORT_IOMUXC_TOP_BASE,    0x30ccU,   1},
    {    GPIO_A11,    4,    PORT_IOMUXC_TOP_BASE,    0x3060U,   1},
    {    GPIO_A11,    5,    PORT_IOMUXC_TOP_BASE,    0x3210U,   1},
    {    GPIO_A12,    2,    PORT_IOMUXC_TOP_BASE,    0x3030U,   2},
    {    GPIO_A12,    3,    PORT_IOMUXC_TOP_BASE,    0x30d4U,   1},
    {    GPIO_A12,    4,    PORT_IOMUXC_TOP_BASE,    0x3290U,   0},
    {    GPIO_A12,    5,    PORT_IOMUXC_TOP_BASE,    0x3294U,   0},
    {    GPIO_A13,    3,    PORT_IOMUXC_TOP_BASE,    0x30e0U,   1},
    {    GPIO_A13,    4,    PORT_IOMUXC_TOP_BASE,    0x3298U,   0},
    {    GPIO_A13,    5,    PORT_IOMUXC_TOP_BASE,    0x329cU,   0},
    {    GPIO_A14,    2,    PORT_IOMUXC_TOP_BASE,    0x3034U,   2},
    {    GPIO_A14,    3,    PORT_IOMUXC_TOP_BASE,    0x30ecU,   1},
    {    GPIO_A14,    4,    PORT_IOMUXC_TOP_BASE,    0x32a0U,   0},
    {    GPIO_A14,    5,    PORT_IOMUXC_TOP_BASE,    0x32a4U,   0},
    {    GPIO_A15,    3,    PORT_IOMUXC_TOP_BASE,    0x30f8U,   1},
    {    GPIO_A15,    4,    PORT_IOMUXC_TOP_BASE,    0x32a8U,   0},
    {    GPIO_A15,    5,    PORT_IOMUXC_TOP_BASE,    0x32acU,   0},
    {     GPIO_B0,    1,    PORT_IOMUXC_TOP_BASE,    0x3104U,   1},
    {     GPIO_B0,    3,    PORT_IOMUXC_TOP_BASE,    0x3108U,   1},
    {     GPIO_B0,    4,    PORT_IOMUXC_TOP_BASE,    0x32b0U,   0},
    {     GPIO_B0,    5,    PORT_IOMUXC_TOP_BASE,    0x3218U,   1},
    {     GPIO_B1,    1,    PORT_IOMUXC_TOP_BASE,    0x3114U,   1},
    {     GPIO_B1,    3,    PORT_IOMUXC_TOP_BASE,    0x30acU,   1},
    {     GPIO_B1,    4,    PORT_IOMUXC_TOP_BASE,    0x3064U,   1},
    {     GPIO_B1,    5,    PORT_IOMUXC_TOP_BASE,    0x321cU,   1},
    {     GPIO_B2,    1,    PORT_IOMUXC_TOP_BASE,    0x3120U,   1},
    {     GPIO_B2,    2,    PORT_IOMUXC_TOP_BASE,    0x3058U,   1},
    {     GPIO_B2,    3,    PORT_IOMUXC_TOP_BASE,    0x31e4U,   1},
    {     GPIO_B2,    5,    PORT_IOMUXC_TOP_BASE,    0x3220U,   1},
    {     GPIO_B3,    1,    PORT_IOMUXC_TOP_BASE,    0x3130U,   1},
    {     GPIO_B3,    3,    PORT_IOMUXC_TOP_BASE,    0x31ecU,   1},
    {     GPIO_B3,    5,    PORT_IOMUXC_TOP_BASE,    0x3224U,   1},
    {     GPIO_B4,    1,    PORT_IOMUXC_TOP_BASE,    0x313cU,   1},
    {     GPIO_B4,    2,    PORT_IOMUXC_TOP_BASE,    0x305cU,   1},
    {     GPIO_B4,    3,    PORT_IOMUXC_TOP_BASE,    0x31f4U,   1},
    {     GPIO_B4,    5,    PORT_IOMUXC_TOP_BASE,    0x3228U,   1},
    {     GPIO_B4,    7,    PORT_IOMUXC_TOP_BASE,    0x32b4U,   0},
    {     GPIO_B5,    1,    PORT_IOMUXC_TOP_BASE,    0x314cU,   1},
    {     GPIO_B5,    3,    PORT_IOMUXC_TOP_BASE,    0x31fcU,   1},
    {     GPIO_B5,    5,    PORT_IOMUXC_TOP_BASE,    0x322cU,   1},
    {     GPIO_B5,    7,    PORT_IOMUXC_TOP_BASE,    0x32b8U,   0},
    {     GPIO_B6,    3,    PORT_IOMUXC_TOP_BASE,    0x3204U,   1},
    {     GPIO_B6,    4,    PORT_IOMUXC_TOP_BASE,    0x32bcU,   0},
    {     GPIO_B6,    5,    PORT_IOMUXC_TOP_BASE,    0x3294U,   1},
    {     GPIO_B6,    6,    PORT_IOMUXC_TOP_BASE,    0x323cU,   2},
    {     GPIO_B6,    7,    PORT_IOMUXC_TOP_BASE,    0x32c0U,   0},
    {     GPIO_B7,    3,    PORT_IOMUXC_TOP_BASE,    0x320cU,   1},
    {     GPIO_B7,    4,    PORT_IOMUXC_TOP_BASE,    0x3068U,   1},
    {     GPIO_B7,    5,    PORT_IOMUXC_TOP_BASE,    0x329cU,   1},
    {     GPIO_B7,    6,    PORT_IOMUXC_TOP_BASE,    0x3248U,   2},
    {     GPIO_B7,    7,    PORT_IOMUXC_TOP_BASE,    0x32c4U,   0},
    {     GPIO_B8,    3,    PORT_IOMUXC_TOP_BASE,    0x3214U,   1},
    {     GPIO_B8,    4,    PORT_IOMUXC_TOP_BASE,    0x32c8U,   0},
    {     GPIO_B8,    5,    PORT_IOMUXC_TOP_BASE,    0x32a4U,   1},
    {     GPIO_B8,    6,    PORT_IOMUXC_TOP_BASE,    0x327cU,   1},
    {     GPIO_B8,    7,    PORT_IOMUXC_TOP_BASE,    0x32ccU,   0},
    {     GPIO_B9,    3,    PORT_IOMUXC_TOP_BASE,    0x32d0U,   0},
    {     GPIO_B9,    4,    PORT_IOMUXC_TOP_BASE,    0x32d4U,   0},
    {     GPIO_B9,    5,    PORT_IOMUXC_TOP_BASE,    0x32acU,   1},
    {     GPIO_B9,    6,    PORT_IOMUXC_TOP_BASE,    0x3284U,   1},
    {     GPIO_B9,    7,    PORT_IOMUXC_TOP_BASE,    0x32d8U,   0},
    {    GPIO_B10,    2,    PORT_IOMUXC_TOP_BASE,    0x3040U,   2},
    {    GPIO_B10,    3,    PORT_IOMUXC_TOP_BASE,    0x32dcU,   0},
    {    GPIO_B10,    5,    PORT_IOMUXC_TOP_BASE,    0x32e0U,   0},
    {    GPIO_B11,    3,    PORT_IOMUXC_TOP_BASE,    0x32e4U,   0},
    {    GPIO_B11,    5,    PORT_IOMUXC_TOP_BASE,    0x32e8U,   0},
    {    GPIO_B12,    2,    PORT_IOMUXC_TOP_BASE,    0x3044U,   2},
    {    GPIO_B12,    3,    PORT_IOMUXC_TOP_BASE,    0x32ecU,   0},
    {    GPIO_B12,    5,    PORT_IOMUXC_TOP_BASE,    0x32f0U,   0},
    {    GPIO_B12,    6,    PORT_IOMUXC_TOP_BASE,    0x325cU,   1},
    {    GPIO_B13,    3,    PORT_IOMUXC_TOP_BASE,    0x32f4U,   0},
    {    GPIO_B13,    5,    PORT_IOMUXC_TOP_BASE,    0x32f8U,   0},
    {    GPIO_B13,    6,    PORT_IOMUXC_TOP_BASE,    0x3268U,   1},
    {    GPIO_B14,    3,    PORT_IOMUXC_TOP_BASE,    0x32fcU,   0},
    {    GPIO_B14,    4,    PORT_IOMUXC_TOP_BASE,    0x3300U,   0},
    {    GPIO_B14,    5,    PORT_IOMUXC_TOP_BASE,    0x3304U,   0},
    {    GPIO_B15,    3,    PORT_IOMUXC_TOP_BASE,    0x3308U,   0},
    {    GPIO_B15,    4,    PORT_IOMUXC_TOP_BASE,    0x330cU,   0},
    {    GPIO_B15,    5,    PORT_IOMUXC_TOP_BASE,    0x3310U,   0},
    {     GPIO_C0,    3,    PORT_IOMUXC_TOP_BASE,    0x32dcU,   1},
    {     GPIO_C0,    4,    PORT_IOMUXC_TOP_BASE,    0x3314U,   0},
    {     GPIO_C0,    5,    PORT_IOMUXC_TOP_BASE,    0x32e0U,   1},
    {     GPIO_C1,    3,    PORT_IOMUXC_TOP_BASE,    0x32e4U,   1},
    {     GPIO_C1,    4,    PORT_IOMUXC_TOP_BASE,    0x306cU,   1},
    {     GPIO_C1,    5,    PORT_IOMUXC_TOP_BASE,    0x32e8U,   1},
    {     GPIO_C2,    3,    PORT_IOMUXC_TOP_BASE,    0x32ecU,   1},
    {     GPIO_C2,    4,    PORT_IOMUXC_TOP_BASE,    0x3318U,   0},
    {     GPIO_C2,    5,    PORT_IOMUXC_TOP_BASE,    0x32f0U,   1},
    {     GPIO_C3,    3,    PORT_IOMUXC_TOP_BASE,    0x32f4U,   1},
    {     GPIO_C3,    4,    PORT_IOMUXC_TOP_BASE,    0x3070U,   1},
    {     GPIO_C3,    5,    PORT_IOMUXC_TOP_BASE,    0x32f8U,   1},
    {     GPIO_C4,    2,    PORT_IOMUXC_TOP_BASE,    0x3000U,   2},
    {     GPIO_C4,    3,    PORT_IOMUXC_TOP_BASE,    0x32fcU,   1},
    {     GPIO_C4,    4,    PORT_IOMUXC_TOP_BASE,    0x331cU,   0},
    {     GPIO_C4,    5,    PORT_IOMUXC_TOP_BASE,    0x3304U,   1},
    {     GPIO_C5,    3,    PORT_IOMUXC_TOP_BASE,    0x3308U,   1},
    {     GPIO_C5,    4,    PORT_IOMUXC_TOP_BASE,    0x3320U,   0},
    {     GPIO_C5,    5,    PORT_IOMUXC_TOP_BASE,    0x3310U,   1},
    {     GPIO_C6,    2,    PORT_IOMUXC_TOP_BASE,    0x3004U,   2},
    {     GPIO_C6,    3,    PORT_IOMUXC_TOP_BASE,    0x32d0U,   1},
    {     GPIO_C6,    4,    PORT_IOMUXC_TOP_BASE,    0x3324U,   0},
    {     GPIO_C6,    5,    PORT_IOMUXC_TOP_BASE,    0x3328U,   0},
    {     GPIO_C7,    3,    PORT_IOMUXC_TOP_BASE,    0x3118U,   1},
    {     GPIO_C7,    4,    PORT_IOMUXC_TOP_BASE,    0x3074U,   1},
    {     GPIO_C7,    5,    PORT_IOMUXC_TOP_BASE,    0x332cU,   0},
    {     GPIO_C8,    3,    PORT_IOMUXC_TOP_BASE,    0x3124U,   1},
    {     GPIO_C8,    4,    PORT_IOMUXC_TOP_BASE,    0x3330U,   0},
    {     GPIO_C8,    5,    PORT_IOMUXC_TOP_BASE,    0x3328U,   1},
    {     GPIO_C9,    3,    PORT_IOMUXC_TOP_BASE,    0x3134U,   1},
    {     GPIO_C9,    4,    PORT_IOMUXC_TOP_BASE,    0x3334U,   0},
    {     GPIO_C9,    5,    PORT_IOMUXC_TOP_BASE,    0x332cU,   1},
    {    GPIO_C10,    2,    PORT_IOMUXC_TOP_BASE,    0x3048U,   2},
    {    GPIO_C10,    3,    PORT_IOMUXC_TOP_BASE,    0x3140U,   1},
    {    GPIO_C10,    5,    PORT_IOMUXC_TOP_BASE,    0x3338U,   0},
    {    GPIO_C11,    3,    PORT_IOMUXC_TOP_BASE,    0x3150U,   1},
    {    GPIO_C11,    5,    PORT_IOMUXC_TOP_BASE,    0x333cU,   0},
    {    GPIO_C12,    3,    PORT_IOMUXC_TOP_BASE,    0x315cU,   1},
    {    GPIO_C12,    4,    PORT_IOMUXC_TOP_BASE,    0x3340U,   0},
    {    GPIO_C12,    5,    PORT_IOMUXC_TOP_BASE,    0x3344U,   0},
    {    GPIO_C13,    3,    PORT_IOMUXC_TOP_BASE,    0x3168U,   1},
    {    GPIO_C13,    4,    PORT_IOMUXC_TOP_BASE,    0x3078U,   1},
    {    GPIO_C13,    5,    PORT_IOMUXC_TOP_BASE,    0x3348U,   0},
    {    GPIO_C14,    2,    PORT_IOMUXC_TOP_BASE,    0x304cU,   2},
    {    GPIO_C14,    3,    PORT_IOMUXC_TOP_BASE,    0x3174U,   1},
    {    GPIO_C14,    4,    PORT_IOMUXC_TOP_BASE,    0x334cU,   0},
    {    GPIO_C14,    5,    PORT_IOMUXC_TOP_BASE,    0x3350U,   0},
    {    GPIO_C15,    3,    PORT_IOMUXC_TOP_BASE,    0x3180U,   1},
    {    GPIO_C15,    4,    PORT_IOMUXC_TOP_BASE,    0x3354U,   0},
    {    GPIO_C15,    5,    PORT_IOMUXC_TOP_BASE,    0x3358U,   0},
    {     GPIO_E0,    1,    PORT_IOMUXC_TOP_BASE,    0x335cU,   0},
    {     GPIO_E0,    3,    PORT_IOMUXC_TOP_BASE,    0x3360U,   0},
    {     GPIO_E0,    5,    PORT_IOMUXC_TOP_BASE,    0x3338U,   1},
    {     GPIO_E1,    1,    PORT_IOMUXC_TOP_BASE,    0x3364U,   0},
    {     GPIO_E1,    3,    PORT_IOMUXC_TOP_BASE,    0x3368U,   0},
    {     GPIO_E1,    5,    PORT_IOMUXC_TOP_BASE,    0x333cU,   1},
    {     GPIO_E2,    1,    PORT_IOMUXC_TOP_BASE,    0x336cU,   0},
    {     GPIO_E2,    3,    PORT_IOMUXC_TOP_BASE,    0x3370U,   0},
    {     GPIO_E2,    5,    PORT_IOMUXC_TOP_BASE,    0x3344U,   1},
    {     GPIO_E3,    1,    PORT_IOMUXC_TOP_BASE,    0x3374U,   0},
    {     GPIO_E3,    3,    PORT_IOMUXC_TOP_BASE,    0x3378U,   0},
    {     GPIO_E3,    5,    PORT_IOMUXC_TOP_BASE,    0x3348U,   1},
    {     GPIO_E4,    1,    PORT_IOMUXC_TOP_BASE,    0x337cU,   0},
    {     GPIO_E4,    3,    PORT_IOMUXC_TOP_BASE,    0x3380U,   0},
    {     GPIO_E4,    4,    PORT_IOMUXC_TOP_BASE,    0x32bcU,   1},
    {     GPIO_E4,    5,    PORT_IOMUXC_TOP_BASE,    0x3350U,   1},
    {     GPIO_E5,    1,    PORT_IOMUXC_TOP_BASE,    0x3384U,   0},
    {     GPIO_E5,    3,    PORT_IOMUXC_TOP_BASE,    0x3388U,   0},
    {     GPIO_E5,    4,    PORT_IOMUXC_TOP_BASE,    0x3068U,   2},
    {     GPIO_E5,    5,    PORT_IOMUXC_TOP_BASE,    0x3358U,   1},
    {     GPIO_E6,    1,    PORT_IOMUXC_TOP_BASE,    0x338cU,   0},
    {     GPIO_E6,    3,    PORT_IOMUXC_TOP_BASE,    0x3390U,   0},
    {     GPIO_E6,    4,    PORT_IOMUXC_TOP_BASE,    0x32c8U,   1},
    {     GPIO_E6,    5,    PORT_IOMUXC_TOP_BASE,    0x3084U,   1},
    {     GPIO_E7,    1,    PORT_IOMUXC_TOP_BASE,    0x3394U,   0},
    {     GPIO_E7,    4,    PORT_IOMUXC_TOP_BASE,    0x32d4U,   1},
    {     GPIO_E7,    5,    PORT_IOMUXC_TOP_BASE,    0x3088U,   1},
    {     GPIO_E8,    2,    PORT_IOMUXC_TOP_BASE,    0x3048U,   3},
    {     GPIO_E8,    5,    PORT_IOMUXC_TOP_BASE,    0x3090U,   1},
    {     GPIO_E9,    5,    PORT_IOMUXC_TOP_BASE,    0x3098U,   1},
    {    GPIO_E10,    2,    PORT_IOMUXC_TOP_BASE,    0x304cU,   3},
    {    GPIO_E10,    4,    PORT_IOMUXC_TOP_BASE,    0x3300U,   1},
    {    GPIO_E10,    5,    PORT_IOMUXC_TOP_BASE,    0x30a0U,   1},
    {    GPIO_E11,    4,    PORT_IOMUXC_TOP_BASE,    0x330cU,   1},
    {    GPIO_E11,    5,    PORT_IOMUXC_TOP_BASE,    0x30a8U,   1},
    {    GPIO_E12,    2,    PORT_IOMUXC_TOP_BASE,    0x3050U,   2},
    {    GPIO_E12,    4,    PORT_IOMUXC_TOP_BASE,    0x3314U,   1},
    {    GPIO_E12,    5,    PORT_IOMUXC_TOP_BASE,    0x30b4U,   1},
    {    GPIO_E13,    4,    PORT_IOMUXC_TOP_BASE,    0x306cU,   2},
    {    GPIO_E13,    5,    PORT_IOMUXC_TOP_BASE,    0x30bcU,   1},
    {    GPIO_E14,    2,    PORT_IOMUXC_TOP_BASE,    0x3054U,   2},
    {    GPIO_E14,    5,    PORT_IOMUXC_TOP_BASE,    0x30c8U,   1},
    {    GPIO_E15,    5,    PORT_IOMUXC_TOP_BASE,    0x30d0U,   1},
    {    GPIO_E16,    5,    PORT_IOMUXC_TOP_BASE,    0x30dcU,   1},
    {    GPIO_E17,    5,    PORT_IOMUXC_TOP_BASE,    0x30e8U,   1},
    {    GPIO_E18,    5,    PORT_IOMUXC_TOP_BASE,    0x30f4U,   1},
    {    GPIO_E19,    5,    PORT_IOMUXC_TOP_BASE,    0x3100U,   1},
    {    GPIO_E20,    5,    PORT_IOMUXC_TOP_BASE,    0x3110U,   1},
    {    GPIO_E21,    5,    PORT_IOMUXC_TOP_BASE,    0x311cU,   1},
    {    GPIO_E22,    5,    PORT_IOMUXC_TOP_BASE,    0x3190U,   1},
    {    GPIO_E23,    5,    PORT_IOMUXC_TOP_BASE,    0x3198U,   1},
    {    GPIO_E24,    5,    PORT_IOMUXC_TOP_BASE,    0x31a4U,   1},
    {    GPIO_E25,    5,    PORT_IOMUXC_TOP_BASE,    0x31b0U,   1},
    {    GPIO_E26,    5,    PORT_IOMUXC_TOP_BASE,    0x31bcU,   1},
    {    GPIO_E27,    5,    PORT_IOMUXC_TOP_BASE,    0x31c8U,   1},
    {    GPIO_E28,    5,    PORT_IOMUXC_TOP_BASE,    0x31d4U,   1},
    {    GPIO_E29,    5,    PORT_IOMUXC_TOP_BASE,    0x31d8U,   1},
    {    GPIO_E30,    5,    PORT_IOMUXC_TOP_BASE,    0x31dcU,   1},
    {    GPIO_E31,    5,    PORT_IOMUXC_TOP_BASE,    0x31e0U,   1},
    {     GPIO_S0,    1,    PORT_IOMUXC_TOP_BASE,    0x3498U,   0},
    {     GPIO_S0,    2,    PORT_IOMUXC_TOP_BASE,    0x349cU,   0},
    {     GPIO_S0,    4,    PORT_IOMUXC_TOP_BASE,    0x3128U,   1},
    {     GPIO_S0,    5,    PORT_IOMUXC_TOP_BASE,    0x34a0U,   0},
    {     GPIO_S0,    6,    PORT_IOMUXC_TOP_BASE,    0x34a4U,   0},
    {     GPIO_S1,    1,    PORT_IOMUXC_TOP_BASE,    0x34a8U,   0},
    {     GPIO_S1,    2,    PORT_IOMUXC_TOP_BASE,    0x34acU,   0},
    {     GPIO_S1,    4,    PORT_IOMUXC_TOP_BASE,    0x3018U,   2},
    {     GPIO_S1,    5,    PORT_IOMUXC_TOP_BASE,    0x34b0U,   0},
    {     GPIO_S1,    6,    PORT_IOMUXC_TOP_BASE,    0x34b4U,   0},
    {     GPIO_S2,    1,    PORT_IOMUXC_TOP_BASE,    0x34b8U,   0},
    {     GPIO_S2,    2,    PORT_IOMUXC_TOP_BASE,    0x3040U,   3},
    {     GPIO_S2,    4,    PORT_IOMUXC_TOP_BASE,    0x3144U,   1},
    {     GPIO_S2,    5,    PORT_IOMUXC_TOP_BASE,    0x34bcU,   0},
    {     GPIO_S2,    6,    PORT_IOMUXC_TOP_BASE,    0x34c0U,   0},
    {     GPIO_S3,    1,    PORT_IOMUXC_TOP_BASE,    0x34c4U,   0},
    {     GPIO_S3,    4,    PORT_IOMUXC_TOP_BASE,    0x3154U,   1},
    {     GPIO_S3,    5,    PORT_IOMUXC_TOP_BASE,    0x34c8U,   0},
    {     GPIO_S3,    6,    PORT_IOMUXC_TOP_BASE,    0x34ccU,   0},
    {     GPIO_S4,    1,    PORT_IOMUXC_TOP_BASE,    0x34d0U,   0},
    {     GPIO_S4,    2,    PORT_IOMUXC_TOP_BASE,    0x3044U,   3},
    {     GPIO_S4,    4,    PORT_IOMUXC_TOP_BASE,    0x3160U,   1},
    {     GPIO_S4,    5,    PORT_IOMUXC_TOP_BASE,    0x34d4U,   0},
    {     GPIO_S4,    6,    PORT_IOMUXC_TOP_BASE,    0x34d8U,   0},
    {     GPIO_S5,    1,    PORT_IOMUXC_TOP_BASE,    0x34dcU,   0},
    {     GPIO_S5,    4,    PORT_IOMUXC_TOP_BASE,    0x316cU,   1},
    {     GPIO_S5,    5,    PORT_IOMUXC_TOP_BASE,    0x34e0U,   0},
    {     GPIO_S5,    6,    PORT_IOMUXC_TOP_BASE,    0x34e4U,   0},
    {     GPIO_S6,    1,    PORT_IOMUXC_TOP_BASE,    0x34e8U,   0},
    {     GPIO_S6,    4,    PORT_IOMUXC_TOP_BASE,    0x3178U,   1},
    {     GPIO_S6,    5,    PORT_IOMUXC_TOP_BASE,    0x34ecU,   0},
    {     GPIO_S6,    6,    PORT_IOMUXC_TOP_BASE,    0x34f0U,   0},
    {     GPIO_S7,    1,    PORT_IOMUXC_TOP_BASE,    0x34f4U,   0},
    {     GPIO_S7,    2,    PORT_IOMUXC_TOP_BASE,    0x34f8U,   0},
    {     GPIO_S7,    4,    PORT_IOMUXC_TOP_BASE,    0x301cU,   2},
    {     GPIO_S7,    5,    PORT_IOMUXC_TOP_BASE,    0x34fcU,   0},
    {     GPIO_S7,    6,    PORT_IOMUXC_TOP_BASE,    0x3500U,   0},
    {     GPIO_S8,    1,    PORT_IOMUXC_TOP_BASE,    0x3504U,   0},
    {     GPIO_S8,    5,    PORT_IOMUXC_TOP_BASE,    0x3424U,   1},
    {     GPIO_S8,    6,    PORT_IOMUXC_TOP_BASE,    0x3508U,   0},
    {     GPIO_S9,    1,    PORT_IOMUXC_TOP_BASE,    0x350cU,   0},
    {     GPIO_S9,    3,    PORT_IOMUXC_TOP_BASE,    0x3510U,   0},
    {     GPIO_S9,    5,    PORT_IOMUXC_TOP_BASE,    0x3428U,   1},
    {     GPIO_S9,    6,    PORT_IOMUXC_TOP_BASE,    0x3514U,   0},
    {    GPIO_S10,    1,    PORT_IOMUXC_TOP_BASE,    0x349cU,   1},
    {    GPIO_S10,    3,    PORT_IOMUXC_TOP_BASE,    0x3518U,   0},
    {    GPIO_S10,    5,    PORT_IOMUXC_TOP_BASE,    0x342cU,   1},
    {    GPIO_S10,    6,    PORT_IOMUXC_TOP_BASE,    0x351cU,   0},
    {    GPIO_S11,    1,    PORT_IOMUXC_TOP_BASE,    0x34acU,   1},
    {    GPIO_S11,    3,    PORT_IOMUXC_TOP_BASE,    0x3520U,   0},
    {    GPIO_S11,    5,    PORT_IOMUXC_TOP_BASE,    0x3430U,   1},
    {    GPIO_S12,    3,    PORT_IOMUXC_TOP_BASE,    0x3524U,   0},
    {    GPIO_S12,    4,    PORT_IOMUXC_TOP_BASE,    0x334cU,   1},
    {    GPIO_S12,    5,    PORT_IOMUXC_TOP_BASE,    0x3488U,   1},
    {    GPIO_S13,    1,    PORT_IOMUXC_TOP_BASE,    0x34f8U,   1},
    {    GPIO_S13,    3,    PORT_IOMUXC_TOP_BASE,    0x3528U,   0},
    {    GPIO_S13,    4,    PORT_IOMUXC_TOP_BASE,    0x3354U,   1},
    {    GPIO_S13,    5,    PORT_IOMUXC_TOP_BASE,    0x348cU,   1},
    {    GPIO_S14,    3,    PORT_IOMUXC_TOP_BASE,    0x352cU,   0},
    {    GPIO_S14,    4,    PORT_IOMUXC_TOP_BASE,    0x3340U,   1},
    {    GPIO_S14,    5,    PORT_IOMUXC_TOP_BASE,    0x3490U,   1},
    {    GPIO_S14,    7,    PORT_IOMUXC_TOP_BASE,    0x325cU,   3},
    {    GPIO_S15,    3,    PORT_IOMUXC_TOP_BASE,    0x3530U,   0},
    {    GPIO_S15,    4,    PORT_IOMUXC_TOP_BASE,    0x3078U,   2},
    {    GPIO_S15,    5,    PORT_IOMUXC_TOP_BASE,    0x3494U,   1},
    {    GPIO_S15,    7,    PORT_IOMUXC_TOP_BASE,    0x3268U,   3},
    {    GPIO_S16,    2,    PORT_IOMUXC_TOP_BASE,    0x3058U,   2},
    {    GPIO_S16,    5,    PORT_IOMUXC_TOP_BASE,    0x3534U,   0},
    {    GPIO_S17,    5,    PORT_IOMUXC_TOP_BASE,    0x3538U,   0},
    {    GPIO_S18,    5,    PORT_IOMUXC_TOP_BASE,    0x353cU,   0},
    {    GPIO_S19,    5,    PORT_IOMUXC_TOP_BASE,    0x3540U,   0},
    {    GPIO_S20,    5,    PORT_IOMUXC_TOP_BASE,    0x3544U,   0},
    {    GPIO_S21,    5,    PORT_IOMUXC_TOP_BASE,    0x3548U,   0},
    {    GPIO_S22,    5,    PORT_IOMUXC_TOP_BASE,    0x354cU,   0},
    {    GPIO_S23,    5,    PORT_IOMUXC_TOP_BASE,    0x3550U,   0},
    {    GPIO_S24,    5,    PORT_IOMUXC_TOP_BASE,    0x3554U,   0},
    {    GPIO_S25,    5,    PORT_IOMUXC_TOP_BASE,    0x3558U,   0},
    {    GPIO_S26,    5,    PORT_IOMUXC_TOP_BASE,    0x355cU,   0},
    {    GPIO_S27,    5,    PORT_IOMUXC_TOP_BASE,    0x3560U,   0},
    {    GPIO_S28,    5,    PORT_IOMUXC_TOP_BASE,    0x3564U,   0},
    {    GPIO_S29,    5,    PORT_IOMUXC_TOP_BASE,    0x3568U,   0},
    {    GPIO_S30,    5,    PORT_IOMUXC_TOP_BASE,    0x356cU,   0},
    {    GPIO_S31,    5,    PORT_IOMUXC_TOP_BASE,    0x3570U,   0},
    {     GPIO_M0,    1,    PORT_IOMUXC_TOP_BASE,    0x3438U,   4},
    {     GPIO_M0,    3,    PORT_IOMUXC_TOP_BASE,    0x3598U,   1},
    {     GPIO_M0,    5,    PORT_IOMUXC_TOP_BASE,    0x33a4U,   3},
    {     GPIO_M0,    6,    PORT_IOMUXC_TOP_BASE,    0x3498U,   1},
    {     GPIO_M1,    1,    PORT_IOMUXC_TOP_BASE,    0x3444U,   2},
    {     GPIO_M1,    3,    PORT_IOMUXC_TOP_BASE,    0x359cU,   1},
    {     GPIO_M1,    5,    PORT_IOMUXC_TOP_BASE,    0x33b4U,   3},
    {     GPIO_M1,    6,    PORT_IOMUXC_TOP_BASE,    0x34a8U,   1},
    {     GPIO_M2,    1,    PORT_IOMUXC_TOP_BASE,    0x344cU,   2},
    {     GPIO_M2,    3,    PORT_IOMUXC_TOP_BASE,    0x35a0U,   1},
    {     GPIO_M2,    5,    PORT_IOMUXC_TOP_BASE,    0x33c4U,   3},
    {     GPIO_M2,    6,    PORT_IOMUXC_TOP_BASE,    0x34b8U,   1},
    {     GPIO_M2,    7,    PORT_IOMUXC_TOP_BASE,    0x3280U,   3},
    {     GPIO_M3,    1,    PORT_IOMUXC_TOP_BASE,    0x3454U,   2},
    {     GPIO_M3,    3,    PORT_IOMUXC_TOP_BASE,    0x35a4U,   1},
    {     GPIO_M3,    5,    PORT_IOMUXC_TOP_BASE,    0x33d0U,   3},
    {     GPIO_M3,    6,    PORT_IOMUXC_TOP_BASE,    0x34c4U,   1},
    {     GPIO_M4,    1,    PORT_IOMUXC_TOP_BASE,    0x345cU,   4},
    {     GPIO_M4,    3,    PORT_IOMUXC_TOP_BASE,    0x35a8U,   1},
    {     GPIO_M4,    5,    PORT_IOMUXC_TOP_BASE,    0x33dcU,   3},
    {     GPIO_M4,    6,    PORT_IOMUXC_TOP_BASE,    0x34d0U,   1},
    {     GPIO_M4,    7,    PORT_IOMUXC_TOP_BASE,    0x328cU,   3},
    {     GPIO_M5,    1,    PORT_IOMUXC_TOP_BASE,    0x3464U,   2},
    {     GPIO_M5,    3,    PORT_IOMUXC_TOP_BASE,    0x35acU,   1},
    {     GPIO_M5,    5,    PORT_IOMUXC_TOP_BASE,    0x33e8U,   3},
    {     GPIO_M5,    6,    PORT_IOMUXC_TOP_BASE,    0x34dcU,   1},
    {     GPIO_M6,    1,    PORT_IOMUXC_TOP_BASE,    0x346cU,   2},
    {     GPIO_M6,    3,    PORT_IOMUXC_TOP_BASE,    0x35b0U,   1},
    {     GPIO_M6,    4,    PORT_IOMUXC_TOP_BASE,    0x3324U,   1},
    {     GPIO_M6,    5,    PORT_IOMUXC_TOP_BASE,    0x33f4U,   3},
    {     GPIO_M6,    6,    PORT_IOMUXC_TOP_BASE,    0x34e8U,   1},
    {     GPIO_M7,    1,    PORT_IOMUXC_TOP_BASE,    0x3474U,   2},
    {     GPIO_M7,    4,    PORT_IOMUXC_TOP_BASE,    0x3074U,   2},
    {     GPIO_M7,    5,    PORT_IOMUXC_TOP_BASE,    0x33fcU,   3},
    {     GPIO_M7,    6,    PORT_IOMUXC_TOP_BASE,    0x34f4U,   1},
    {     GPIO_M8,    2,    PORT_IOMUXC_TOP_BASE,    0x3058U,   3},
    {     GPIO_M8,    4,    PORT_IOMUXC_TOP_BASE,    0x3330U,   1},
    {     GPIO_M8,    5,    PORT_IOMUXC_TOP_BASE,    0x3404U,   1},
    {     GPIO_M8,    6,    PORT_IOMUXC_TOP_BASE,    0x3504U,   1},
    {     GPIO_M9,    4,    PORT_IOMUXC_TOP_BASE,    0x3334U,   1},
    {     GPIO_M9,    5,    PORT_IOMUXC_TOP_BASE,    0x3410U,   1},
    {     GPIO_M9,    6,    PORT_IOMUXC_TOP_BASE,    0x350cU,   1},
    {    GPIO_M10,    2,    PORT_IOMUXC_TOP_BASE,    0x305cU,   3},
    {    GPIO_M10,    5,    PORT_IOMUXC_TOP_BASE,    0x3418U,   1},
    {    GPIO_M10,    6,    PORT_IOMUXC_TOP_BASE,    0x349cU,   2},
    {    GPIO_M11,    5,    PORT_IOMUXC_TOP_BASE,    0x3420U,   1},
    {    GPIO_M11,    6,    PORT_IOMUXC_TOP_BASE,    0x34acU,   2},
    {    GPIO_M12,    2,    PORT_IOMUXC_TOP_BASE,    0x3000U,   4},
    {    GPIO_M12,    5,    PORT_IOMUXC_TOP_BASE,    0x3434U,   1},
    {    GPIO_M13,    5,    PORT_IOMUXC_TOP_BASE,    0x343cU,   1},
    {    GPIO_M13,    6,    PORT_IOMUXC_TOP_BASE,    0x34f8U,   2},
    {    GPIO_M14,    2,    PORT_IOMUXC_TOP_BASE,    0x3004U,   4},
    {    GPIO_M14,    5,    PORT_IOMUXC_TOP_BASE,    0x3448U,   1},
    {    GPIO_M14,    6,    PORT_IOMUXC_TOP_BASE,    0x323cU,   5},
    {    GPIO_M15,    5,    PORT_IOMUXC_TOP_BASE,    0x3450U,   1},
    {    GPIO_M15,    6,    PORT_IOMUXC_TOP_BASE,    0x3248U,   5},
    {    GPIO_M16,    5,    PORT_IOMUXC_TOP_BASE,    0x3458U,   1},
    {    GPIO_M17,    5,    PORT_IOMUXC_TOP_BASE,    0x3460U,   1},
    {    GPIO_M18,    5,    PORT_IOMUXC_TOP_BASE,    0x3468U,   1},
    {    GPIO_M19,    5,    PORT_IOMUXC_TOP_BASE,    0x3470U,   1},
    {    GPIO_M20,    5,    PORT_IOMUXC_TOP_BASE,    0x3478U,   1},
    {    GPIO_M21,    5,    PORT_IOMUXC_TOP_BASE,    0x347cU,   1},
    {    GPIO_M22,    5,    PORT_IOMUXC_TOP_BASE,    0x3480U,   1},
    {    GPIO_M23,    5,    PORT_IOMUXC_TOP_BASE,    0x3484U,   1},
    {    GPIO_M24,    5,    PORT_IOMUXC_TOP_BASE,    0x34a0U,   1},
    {    GPIO_M25,    5,    PORT_IOMUXC_TOP_BASE,    0x34b0U,   1},
    {    GPIO_M26,    5,    PORT_IOMUXC_TOP_BASE,    0x34bcU,   1},
    {    GPIO_M27,    5,    PORT_IOMUXC_TOP_BASE,    0x34c8U,   1},
    {    GPIO_M28,    5,    PORT_IOMUXC_TOP_BASE,    0x34d4U,   1},
    {    GPIO_M29,    5,    PORT_IOMUXC_TOP_BASE,    0x34e0U,   1},
    {    GPIO_M30,    5,    PORT_IOMUXC_TOP_BASE,    0x34ecU,   1},
    {    GPIO_M31,    5,    PORT_IOMUXC_TOP_BASE,    0x34fcU,   1},
    {     GPIO_X0,    1,    PORT_IOMUXC_TOP_BASE,    0x3398U,   0},
    {     GPIO_X0,    3,    PORT_IOMUXC_TOP_BASE,    0x339cU,   0},
    {     GPIO_X0,    4,    PORT_IOMUXC_TOP_BASE,    0x33a0U,   0},
    {     GPIO_X0,    5,    PORT_IOMUXC_TOP_BASE,    0x33a4U,   0},
    {     GPIO_X0,    7,    PORT_IOMUXC_TOP_BASE,    0x335cU,   1},
    {     GPIO_X1,    1,    PORT_IOMUXC_TOP_BASE,    0x33a8U,   0},
    {     GPIO_X1,    3,    PORT_IOMUXC_TOP_BASE,    0x33acU,   0},
    {     GPIO_X1,    4,    PORT_IOMUXC_TOP_BASE,    0x33b0U,   0},
    {     GPIO_X1,    5,    PORT_IOMUXC_TOP_BASE,    0x33b4U,   0},
    {     GPIO_X1,    7,    PORT_IOMUXC_TOP_BASE,    0x3364U,   1},
    {     GPIO_X2,    1,    PORT_IOMUXC_TOP_BASE,    0x33b8U,   0},
    {     GPIO_X2,    3,    PORT_IOMUXC_TOP_BASE,    0x33bcU,   0},
    {     GPIO_X2,    4,    PORT_IOMUXC_TOP_BASE,    0x33c0U,   0},
    {     GPIO_X2,    5,    PORT_IOMUXC_TOP_BASE,    0x33c4U,   0},
    {     GPIO_X2,    7,    PORT_IOMUXC_TOP_BASE,    0x336cU,   1},
    {     GPIO_X3,    1,    PORT_IOMUXC_TOP_BASE,    0x33c8U,   0},
    {     GPIO_X3,    3,    PORT_IOMUXC_TOP_BASE,    0x33ccU,   0},
    {     GPIO_X3,    4,    PORT_IOMUXC_TOP_BASE,    0x307cU,   1},
    {     GPIO_X3,    5,    PORT_IOMUXC_TOP_BASE,    0x33d0U,   0},
    {     GPIO_X3,    7,    PORT_IOMUXC_TOP_BASE,    0x3374U,   1},
    {     GPIO_X4,    1,    PORT_IOMUXC_TOP_BASE,    0x33d4U,   0},
    {     GPIO_X4,    3,    PORT_IOMUXC_TOP_BASE,    0x33d8U,   0},
    {     GPIO_X4,    5,    PORT_IOMUXC_TOP_BASE,    0x33dcU,   0},
    {     GPIO_X4,    7,    PORT_IOMUXC_TOP_BASE,    0x337cU,   1},
    {     GPIO_X5,    1,    PORT_IOMUXC_TOP_BASE,    0x33e0U,   0},
    {     GPIO_X5,    2,    PORT_IOMUXC_TOP_BASE,    0x3030U,   3},
    {     GPIO_X5,    3,    PORT_IOMUXC_TOP_BASE,    0x33e4U,   0},
    {     GPIO_X5,    4,    PORT_IOMUXC_TOP_BASE,    0x3080U,   1},
    {     GPIO_X5,    5,    PORT_IOMUXC_TOP_BASE,    0x33e8U,   0},
    {     GPIO_X5,    7,    PORT_IOMUXC_TOP_BASE,    0x3384U,   1},
    {     GPIO_X6,    1,    PORT_IOMUXC_TOP_BASE,    0x33ecU,   0},
    {     GPIO_X6,    3,    PORT_IOMUXC_TOP_BASE,    0x33f0U,   0},
    {     GPIO_X6,    4,    PORT_IOMUXC_TOP_BASE,    0x3008U,   2},
    {     GPIO_X6,    5,    PORT_IOMUXC_TOP_BASE,    0x33f4U,   0},
    {     GPIO_X6,    7,    PORT_IOMUXC_TOP_BASE,    0x338cU,   1},
    {     GPIO_X7,    1,    PORT_IOMUXC_TOP_BASE,    0x33f8U,   0},
    {     GPIO_X7,    2,    PORT_IOMUXC_TOP_BASE,    0x3034U,   3},
    {     GPIO_X7,    3,    PORT_IOMUXC_TOP_BASE,    0x31c0U,   1},
    {     GPIO_X7,    4,    PORT_IOMUXC_TOP_BASE,    0x308cU,   1},
    {     GPIO_X7,    5,    PORT_IOMUXC_TOP_BASE,    0x33fcU,   0},
    {     GPIO_X7,    7,    PORT_IOMUXC_TOP_BASE,    0x3394U,   1},
    {     GPIO_X8,    1,    PORT_IOMUXC_TOP_BASE,    0x3400U,   0},
    {     GPIO_X8,    3,    PORT_IOMUXC_TOP_BASE,    0x31b4U,   1},
    {     GPIO_X8,    4,    PORT_IOMUXC_TOP_BASE,    0x3094U,   1},
    {     GPIO_X8,    5,    PORT_IOMUXC_TOP_BASE,    0x3404U,   0},
    {     GPIO_X8,    7,    PORT_IOMUXC_TOP_BASE,    0x3408U,   0},
    {     GPIO_X9,    1,    PORT_IOMUXC_TOP_BASE,    0x340cU,   0},
    {     GPIO_X9,    3,    PORT_IOMUXC_TOP_BASE,    0x3194U,   1},
    {     GPIO_X9,    5,    PORT_IOMUXC_TOP_BASE,    0x3410U,   0},
    {     GPIO_X9,    6,    PORT_IOMUXC_TOP_BASE,    0x325cU,   2},
    {    GPIO_X10,    1,    PORT_IOMUXC_TOP_BASE,    0x3414U,   0},
    {    GPIO_X10,    3,    PORT_IOMUXC_TOP_BASE,    0x319cU,   1},
    {    GPIO_X10,    4,    PORT_IOMUXC_TOP_BASE,    0x30b0U,   1},
    {    GPIO_X10,    5,    PORT_IOMUXC_TOP_BASE,    0x3418U,   0},
    {    GPIO_X10,    6,    PORT_IOMUXC_TOP_BASE,    0x3268U,   2},
    {    GPIO_X10,    7,    PORT_IOMUXC_TOP_BASE,    0x341cU,   0},
    {    GPIO_X11,    3,    PORT_IOMUXC_TOP_BASE,    0x31a8U,   1},
    {    GPIO_X11,    4,    PORT_IOMUXC_TOP_BASE,    0x300cU,   2},
    {    GPIO_X11,    5,    PORT_IOMUXC_TOP_BASE,    0x3420U,   0},
    {    GPIO_X12,    1,    PORT_IOMUXC_TOP_BASE,    0x32b4U,   1},
    {    GPIO_X12,    3,    PORT_IOMUXC_TOP_BASE,    0x31ccU,   1},
    {    GPIO_X12,    4,    PORT_IOMUXC_TOP_BASE,    0x309cU,   1},
    {    GPIO_X12,    5,    PORT_IOMUXC_TOP_BASE,    0x3424U,   0},
    {    GPIO_X13,    1,    PORT_IOMUXC_TOP_BASE,    0x32b8U,   1},
    {    GPIO_X13,    3,    PORT_IOMUXC_TOP_BASE,    0x3188U,   1},
    {    GPIO_X13,    4,    PORT_IOMUXC_TOP_BASE,    0x30a4U,   1},
    {    GPIO_X13,    5,    PORT_IOMUXC_TOP_BASE,    0x3428U,   0},
    {    GPIO_X14,    1,    PORT_IOMUXC_TOP_BASE,    0x32c0U,   1},
    {    GPIO_X14,    5,    PORT_IOMUXC_TOP_BASE,    0x342cU,   0},
    {    GPIO_X15,    5,    PORT_IOMUXC_TOP_BASE,    0x3430U,   0},
    {     GPIO_Y0,    3,    PORT_IOMUXC_TOP_BASE,    0x3360U,   1},
    {     GPIO_Y0,    4,    PORT_IOMUXC_TOP_BASE,    0x30c4U,   1},
    {     GPIO_Y0,    5,    PORT_IOMUXC_TOP_BASE,    0x3434U,   0},
    {     GPIO_Y0,    7,    PORT_IOMUXC_TOP_BASE,    0x3438U,   0},
    {     GPIO_Y1,    3,    PORT_IOMUXC_TOP_BASE,    0x3368U,   1},
    {     GPIO_Y1,    4,    PORT_IOMUXC_TOP_BASE,    0x3010U,   2},
    {     GPIO_Y1,    5,    PORT_IOMUXC_TOP_BASE,    0x343cU,   0},
    {     GPIO_Y1,    6,    PORT_IOMUXC_TOP_BASE,    0x3440U,   0},
    {     GPIO_Y1,    7,    PORT_IOMUXC_TOP_BASE,    0x3444U,   0},
    {     GPIO_Y2,    3,    PORT_IOMUXC_TOP_BASE,    0x3370U,   1},
    {     GPIO_Y2,    4,    PORT_IOMUXC_TOP_BASE,    0x30d8U,   1},
    {     GPIO_Y2,    5,    PORT_IOMUXC_TOP_BASE,    0x3448U,   0},
    {     GPIO_Y2,    6,    PORT_IOMUXC_TOP_BASE,    0x327cU,   2},
    {     GPIO_Y2,    7,    PORT_IOMUXC_TOP_BASE,    0x344cU,   0},
    {     GPIO_Y3,    3,    PORT_IOMUXC_TOP_BASE,    0x3378U,   1},
    {     GPIO_Y3,    4,    PORT_IOMUXC_TOP_BASE,    0x30e4U,   1},
    {     GPIO_Y3,    5,    PORT_IOMUXC_TOP_BASE,    0x3450U,   0},
    {     GPIO_Y3,    6,    PORT_IOMUXC_TOP_BASE,    0x3284U,   2},
    {     GPIO_Y3,    7,    PORT_IOMUXC_TOP_BASE,    0x3454U,   0},
    {     GPIO_Y4,    2,    PORT_IOMUXC_TOP_BASE,    0x3038U,   3},
    {     GPIO_Y4,    3,    PORT_IOMUXC_TOP_BASE,    0x3380U,   1},
    {     GPIO_Y4,    5,    PORT_IOMUXC_TOP_BASE,    0x3458U,   0},
    {     GPIO_Y4,    6,    PORT_IOMUXC_TOP_BASE,    0x323cU,   3},
    {     GPIO_Y4,    7,    PORT_IOMUXC_TOP_BASE,    0x345cU,   0},
    {     GPIO_Y5,    3,    PORT_IOMUXC_TOP_BASE,    0x3388U,   1},
    {     GPIO_Y5,    5,    PORT_IOMUXC_TOP_BASE,    0x3460U,   0},
    {     GPIO_Y5,    6,    PORT_IOMUXC_TOP_BASE,    0x3248U,   3},
    {     GPIO_Y5,    7,    PORT_IOMUXC_TOP_BASE,    0x3464U,   0},
    {     GPIO_Y6,    2,    PORT_IOMUXC_TOP_BASE,    0x303cU,   3},
    {     GPIO_Y6,    3,    PORT_IOMUXC_TOP_BASE,    0x3390U,   1},
    {     GPIO_Y6,    5,    PORT_IOMUXC_TOP_BASE,    0x3468U,   0},
    {     GPIO_Y6,    7,    PORT_IOMUXC_TOP_BASE,    0x346cU,   0},
    {     GPIO_Y7,    3,    PORT_IOMUXC_TOP_BASE,    0x326cU,   1},
    {     GPIO_Y7,    5,    PORT_IOMUXC_TOP_BASE,    0x3470U,   0},
    {     GPIO_Y7,    7,    PORT_IOMUXC_TOP_BASE,    0x3474U,   0},
    {     GPIO_Y8,    3,    PORT_IOMUXC_TOP_BASE,    0x3260U,   1},
    {     GPIO_Y8,    4,    PORT_IOMUXC_TOP_BASE,    0x30f0U,   1},
    {     GPIO_Y8,    5,    PORT_IOMUXC_TOP_BASE,    0x3478U,   0},
    {     GPIO_Y8,    7,    PORT_IOMUXC_TOP_BASE,    0x341cU,   1},
    {     GPIO_Y9,    3,    PORT_IOMUXC_TOP_BASE,    0x3240U,   1},
    {     GPIO_Y9,    4,    PORT_IOMUXC_TOP_BASE,    0x30fcU,   1},
    {     GPIO_Y9,    5,    PORT_IOMUXC_TOP_BASE,    0x347cU,   0},
    {     GPIO_Y9,    6,    PORT_IOMUXC_TOP_BASE,    0x328cU,   1},
    {    GPIO_Y10,    3,    PORT_IOMUXC_TOP_BASE,    0x324cU,   1},
    {    GPIO_Y10,    4,    PORT_IOMUXC_TOP_BASE,    0x310cU,   1},
    {    GPIO_Y10,    5,    PORT_IOMUXC_TOP_BASE,    0x3480U,   0},
    {    GPIO_Y10,    6,    PORT_IOMUXC_TOP_BASE,    0x3280U,   1},
    {    GPIO_Y10,    7,    PORT_IOMUXC_TOP_BASE,    0x3408U,   1},
    {    GPIO_Y11,    3,    PORT_IOMUXC_TOP_BASE,    0x3254U,   1},
    {    GPIO_Y11,    4,    PORT_IOMUXC_TOP_BASE,    0x3014U,   2},
    {    GPIO_Y11,    5,    PORT_IOMUXC_TOP_BASE,    0x3484U,   0},
    {    GPIO_Y12,    1,    PORT_IOMUXC_TOP_BASE,    0x32c4U,   1},
    {    GPIO_Y12,    2,    PORT_IOMUXC_TOP_BASE,    0x3050U,   3},
    {    GPIO_Y12,    3,    PORT_IOMUXC_TOP_BASE,    0x3278U,   1},
    {    GPIO_Y12,    5,    PORT_IOMUXC_TOP_BASE,    0x3488U,   0},
    {    GPIO_Y13,    1,    PORT_IOMUXC_TOP_BASE,    0x32ccU,   1},
    {    GPIO_Y13,    3,    PORT_IOMUXC_TOP_BASE,    0x3274U,   1},
    {    GPIO_Y13,    5,    PORT_IOMUXC_TOP_BASE,    0x348cU,   0},
    {    GPIO_Y14,    1,    PORT_IOMUXC_TOP_BASE,    0x32d8U,   1},
    {    GPIO_Y14,    2,    PORT_IOMUXC_TOP_BASE,    0x3054U,   3},
    {    GPIO_Y14,    5,    PORT_IOMUXC_TOP_BASE,    0x3490U,   0},
    {    GPIO_Y15,    5,    PORT_IOMUXC_TOP_BASE,    0x3494U,   0},
    {     GPIO_H0,    1,    PORT_IOMUXC_TOP_BASE,    0x351cU,   1},
    {     GPIO_H0,    2,    PORT_IOMUXC_TOP_BASE,    0x3030U,   4},
    {     GPIO_H0,    4,    PORT_IOMUXC_TOP_BASE,    0x33a0U,   1},
    {     GPIO_H0,    5,    PORT_IOMUXC_TOP_BASE,    0x3574U,   0},
    {     GPIO_H0,    7,    PORT_IOMUXC_TOP_BASE,    0x335cU,   2},
    {     GPIO_H1,    4,    PORT_IOMUXC_TOP_BASE,    0x33b0U,   1},
    {     GPIO_H1,    5,    PORT_IOMUXC_TOP_BASE,    0x3578U,   0},
    {     GPIO_H1,    7,    PORT_IOMUXC_TOP_BASE,    0x3364U,   2},
    {     GPIO_H2,    1,    PORT_IOMUXC_TOP_BASE,    0x3514U,   1},
    {     GPIO_H2,    2,    PORT_IOMUXC_TOP_BASE,    0x3034U,   4},
    {     GPIO_H2,    4,    PORT_IOMUXC_TOP_BASE,    0x33c0U,   1},
    {     GPIO_H2,    5,    PORT_IOMUXC_TOP_BASE,    0x357cU,   0},
    {     GPIO_H2,    7,    PORT_IOMUXC_TOP_BASE,    0x336cU,   2},
    {     GPIO_H3,    1,    PORT_IOMUXC_TOP_BASE,    0x3508U,   1},
    {     GPIO_H3,    4,    PORT_IOMUXC_TOP_BASE,    0x307cU,   2},
    {     GPIO_H3,    5,    PORT_IOMUXC_TOP_BASE,    0x3580U,   0},
    {     GPIO_H3,    7,    PORT_IOMUXC_TOP_BASE,    0x3374U,   2},
    {     GPIO_H4,    1,    PORT_IOMUXC_TOP_BASE,    0x3500U,   1},
    {     GPIO_H4,    2,    PORT_IOMUXC_TOP_BASE,    0x3038U,   4},
    {     GPIO_H4,    4,    PORT_IOMUXC_TOP_BASE,    0x31a0U,   1},
    {     GPIO_H4,    5,    PORT_IOMUXC_TOP_BASE,    0x3584U,   0},
    {     GPIO_H4,    7,    PORT_IOMUXC_TOP_BASE,    0x337cU,   2},
    {     GPIO_H5,    1,    PORT_IOMUXC_TOP_BASE,    0x34f0U,   1},
    {     GPIO_H5,    4,    PORT_IOMUXC_TOP_BASE,    0x31acU,   1},
    {     GPIO_H5,    5,    PORT_IOMUXC_TOP_BASE,    0x3588U,   0},
    {     GPIO_H5,    7,    PORT_IOMUXC_TOP_BASE,    0x3384U,   2},
    {     GPIO_H6,    1,    PORT_IOMUXC_TOP_BASE,    0x34e4U,   1},
    {     GPIO_H6,    2,    PORT_IOMUXC_TOP_BASE,    0x303cU,   4},
    {     GPIO_H6,    4,    PORT_IOMUXC_TOP_BASE,    0x318cU,   1},
    {     GPIO_H6,    5,    PORT_IOMUXC_TOP_BASE,    0x358cU,   0},
    {     GPIO_H6,    7,    PORT_IOMUXC_TOP_BASE,    0x338cU,   2},
    {     GPIO_H7,    1,    PORT_IOMUXC_TOP_BASE,    0x34d8U,   1},
    {     GPIO_H7,    3,    PORT_IOMUXC_TOP_BASE,    0x3590U,   0},
    {     GPIO_H7,    4,    PORT_IOMUXC_TOP_BASE,    0x3020U,   2},
    {     GPIO_H7,    5,    PORT_IOMUXC_TOP_BASE,    0x3594U,   0},
    {     GPIO_H7,    7,    PORT_IOMUXC_TOP_BASE,    0x3394U,   2},
    {     GPIO_H8,    1,    PORT_IOMUXC_TOP_BASE,    0x34ccU,   1},
    {     GPIO_H8,    2,    PORT_IOMUXC_TOP_BASE,    0x323cU,   4},
    {     GPIO_H8,    5,    PORT_IOMUXC_TOP_BASE,    0x33a4U,   1},
    {     GPIO_H8,    7,    PORT_IOMUXC_TOP_BASE,    0x3438U,   1},
    {     GPIO_H9,    1,    PORT_IOMUXC_TOP_BASE,    0x34c0U,   1},
    {     GPIO_H9,    2,    PORT_IOMUXC_TOP_BASE,    0x3248U,   4},
    {     GPIO_H9,    3,    PORT_IOMUXC_TOP_BASE,    0x33acU,   1},
    {     GPIO_H9,    5,    PORT_IOMUXC_TOP_BASE,    0x33b4U,   1},
    {     GPIO_H9,    7,    PORT_IOMUXC_TOP_BASE,    0x3444U,   1},
    {    GPIO_H10,    1,    PORT_IOMUXC_TOP_BASE,    0x34a4U,   1},
    {    GPIO_H10,    3,    PORT_IOMUXC_TOP_BASE,    0x33ccU,   1},
    {    GPIO_H10,    5,    PORT_IOMUXC_TOP_BASE,    0x33c4U,   1},
    {    GPIO_H10,    7,    PORT_IOMUXC_TOP_BASE,    0x344cU,   1},
    {    GPIO_H11,    1,    PORT_IOMUXC_TOP_BASE,    0x34b4U,   1},
    {    GPIO_H11,    3,    PORT_IOMUXC_TOP_BASE,    0x33d8U,   1},
    {    GPIO_H11,    5,    PORT_IOMUXC_TOP_BASE,    0x33d0U,   1},
    {    GPIO_H11,    7,    PORT_IOMUXC_TOP_BASE,    0x3454U,   1},
    {    GPIO_H12,    3,    PORT_IOMUXC_TOP_BASE,    0x33bcU,   1},
    {    GPIO_H12,    4,    PORT_IOMUXC_TOP_BASE,    0x31d0U,   1},
    {    GPIO_H12,    5,    PORT_IOMUXC_TOP_BASE,    0x33dcU,   1},
    {    GPIO_H12,    7,    PORT_IOMUXC_TOP_BASE,    0x345cU,   1},
    {    GPIO_H13,    3,    PORT_IOMUXC_TOP_BASE,    0x339cU,   1},
    {    GPIO_H13,    4,    PORT_IOMUXC_TOP_BASE,    0x3024U,   2},
    {    GPIO_H13,    5,    PORT_IOMUXC_TOP_BASE,    0x33e8U,   1},
    {    GPIO_H13,    7,    PORT_IOMUXC_TOP_BASE,    0x3464U,   1},
    {    GPIO_H14,    2,    PORT_IOMUXC_TOP_BASE,    0x305cU,   2},
    {    GPIO_H14,    3,    PORT_IOMUXC_TOP_BASE,    0x33e4U,   1},
    {    GPIO_H14,    4,    PORT_IOMUXC_TOP_BASE,    0x31b8U,   1},
    {    GPIO_H14,    5,    PORT_IOMUXC_TOP_BASE,    0x33f4U,   1},
    {    GPIO_H14,    7,    PORT_IOMUXC_TOP_BASE,    0x346cU,   1},
    {    GPIO_H15,    3,    PORT_IOMUXC_TOP_BASE,    0x33f0U,   1},
    {    GPIO_H15,    4,    PORT_IOMUXC_TOP_BASE,    0x31c4U,   1},
    {    GPIO_H15,    5,    PORT_IOMUXC_TOP_BASE,    0x33fcU,   1},
    {    GPIO_H15,    7,    PORT_IOMUXC_TOP_BASE,    0x3474U,   1},
    {     GPIO_G0,    2,    PORT_IOMUXC_TOP_BASE,    0x337cU,   3},
    {     GPIO_G0,    3,    PORT_IOMUXC_TOP_BASE,    0x3598U,   0},
    {     GPIO_G0,    5,    PORT_IOMUXC_TOP_BASE,    0x3534U,   1},
    {     GPIO_G1,    2,    PORT_IOMUXC_TOP_BASE,    0x325cU,   4},
    {     GPIO_G1,    3,    PORT_IOMUXC_TOP_BASE,    0x359cU,   0},
    {     GPIO_G1,    5,    PORT_IOMUXC_TOP_BASE,    0x3538U,   1},
    {     GPIO_G2,    2,    PORT_IOMUXC_TOP_BASE,    0x3268U,   4},
    {     GPIO_G2,    3,    PORT_IOMUXC_TOP_BASE,    0x35a0U,   0},
    {     GPIO_G2,    5,    PORT_IOMUXC_TOP_BASE,    0x353cU,   1},
    {     GPIO_G3,    2,    PORT_IOMUXC_TOP_BASE,    0x3408U,   2},
    {     GPIO_G3,    3,    PORT_IOMUXC_TOP_BASE,    0x35a4U,   0},
    {     GPIO_G3,    5,    PORT_IOMUXC_TOP_BASE,    0x3540U,   1},
    {     GPIO_G4,    3,    PORT_IOMUXC_TOP_BASE,    0x35a8U,   0},
    {     GPIO_G4,    4,    PORT_IOMUXC_TOP_BASE,    0x3230U,   1},
    {     GPIO_G4,    5,    PORT_IOMUXC_TOP_BASE,    0x3544U,   1},
    {     GPIO_G5,    2,    PORT_IOMUXC_TOP_BASE,    0x327cU,   3},
    {     GPIO_G5,    3,    PORT_IOMUXC_TOP_BASE,    0x35acU,   0},
    {     GPIO_G5,    4,    PORT_IOMUXC_TOP_BASE,    0x3028U,   2},
    {     GPIO_G5,    5,    PORT_IOMUXC_TOP_BASE,    0x3548U,   1},
    {     GPIO_G6,    2,    PORT_IOMUXC_TOP_BASE,    0x335cU,   3},
    {     GPIO_G6,    3,    PORT_IOMUXC_TOP_BASE,    0x35b0U,   0},
    {     GPIO_G6,    4,    PORT_IOMUXC_TOP_BASE,    0x3244U,   1},
    {     GPIO_G6,    5,    PORT_IOMUXC_TOP_BASE,    0x354cU,   1},
    {     GPIO_G7,    2,    PORT_IOMUXC_TOP_BASE,    0x3284U,   3},
    {     GPIO_G7,    4,    PORT_IOMUXC_TOP_BASE,    0x3250U,   1},
    {     GPIO_G7,    5,    PORT_IOMUXC_TOP_BASE,    0x3550U,   1},
    {     GPIO_G8,    4,    PORT_IOMUXC_TOP_BASE,    0x3258U,   1},
    {     GPIO_G8,    5,    PORT_IOMUXC_TOP_BASE,    0x3554U,   1},
    {     GPIO_G9,    4,    PORT_IOMUXC_TOP_BASE,    0x3264U,   1},
    {     GPIO_G9,    5,    PORT_IOMUXC_TOP_BASE,    0x3558U,   1},
    {    GPIO_G10,    4,    PORT_IOMUXC_TOP_BASE,    0x3270U,   1},
    {    GPIO_G10,    5,    PORT_IOMUXC_TOP_BASE,    0x355cU,   1},
    {    GPIO_G11,    3,    PORT_IOMUXC_TOP_BASE,    0x3590U,   1},
    {    GPIO_G11,    4,    PORT_IOMUXC_TOP_BASE,    0x302cU,   2},
    {    GPIO_G11,    5,    PORT_IOMUXC_TOP_BASE,    0x3560U,   1},
    {    GPIO_G12,    1,    PORT_IOMUXC_TOP_BASE,    0x3408U,   3},
    {    GPIO_G12,    5,    PORT_IOMUXC_TOP_BASE,    0x33a4U,   2},
    {    GPIO_G13,    5,    PORT_IOMUXC_TOP_BASE,    0x33b4U,   2},
    {    GPIO_G14,    1,    PORT_IOMUXC_TOP_BASE,    0x335cU,   4},
    {    GPIO_G14,    5,    PORT_IOMUXC_TOP_BASE,    0x33c4U,   2},
    {    GPIO_G15,    1,    PORT_IOMUXC_TOP_BASE,    0x337cU,   4},
    {    GPIO_G15,    5,    PORT_IOMUXC_TOP_BASE,    0x33d0U,   2},
    {    GPIO_G16,    2,    PORT_IOMUXC_TOP_BASE,    0x345cU,   2},
    {    GPIO_G16,    3,    PORT_IOMUXC_TOP_BASE,    0x3524U,   1},
    {    GPIO_G16,    4,    PORT_IOMUXC_TOP_BASE,    0x3290U,   1},
    {    GPIO_G16,    5,    PORT_IOMUXC_TOP_BASE,    0x3564U,   1},
    {    GPIO_G16,    6,    PORT_IOMUXC_TOP_BASE,    0x325cU,   5},
    {    GPIO_G17,    2,    PORT_IOMUXC_TOP_BASE,    0x3000U,   3},
    {    GPIO_G17,    3,    PORT_IOMUXC_TOP_BASE,    0x3528U,   1},
    {    GPIO_G17,    4,    PORT_IOMUXC_TOP_BASE,    0x3298U,   1},
    {    GPIO_G17,    5,    PORT_IOMUXC_TOP_BASE,    0x3568U,   1},
    {    GPIO_G17,    6,    PORT_IOMUXC_TOP_BASE,    0x3268U,   5},
    {    GPIO_G18,    3,    PORT_IOMUXC_TOP_BASE,    0x352cU,   1},
    {    GPIO_G18,    4,    PORT_IOMUXC_TOP_BASE,    0x3288U,   1},
    {    GPIO_G18,    5,    PORT_IOMUXC_TOP_BASE,    0x356cU,   1},
    {    GPIO_G18,    7,    PORT_IOMUXC_TOP_BASE,    0x3280U,   2},
    {    GPIO_G19,    2,    PORT_IOMUXC_TOP_BASE,    0x341cU,   2},
    {    GPIO_G19,    3,    PORT_IOMUXC_TOP_BASE,    0x3530U,   1},
    {    GPIO_G19,    4,    PORT_IOMUXC_TOP_BASE,    0x3060U,   2},
    {    GPIO_G19,    5,    PORT_IOMUXC_TOP_BASE,    0x3570U,   1},
    {    GPIO_G20,    3,    PORT_IOMUXC_TOP_BASE,    0x3510U,   1},
    {    GPIO_G20,    5,    PORT_IOMUXC_TOP_BASE,    0x3574U,   1},
    {    GPIO_G20,    7,    PORT_IOMUXC_TOP_BASE,    0x328cU,   2},
    {    GPIO_G21,    2,    PORT_IOMUXC_TOP_BASE,    0x314cU,   2},
    {    GPIO_G21,    3,    PORT_IOMUXC_TOP_BASE,    0x3518U,   1},
    {    GPIO_G21,    5,    PORT_IOMUXC_TOP_BASE,    0x3578U,   1},
    {    GPIO_G21,    6,    PORT_IOMUXC_TOP_BASE,    0x327cU,   4},
    {    GPIO_G22,    2,    PORT_IOMUXC_TOP_BASE,    0x3438U,   2},
    {    GPIO_G22,    3,    PORT_IOMUXC_TOP_BASE,    0x3520U,   1},
    {    GPIO_G22,    5,    PORT_IOMUXC_TOP_BASE,    0x357cU,   1},
    {    GPIO_G22,    6,    PORT_IOMUXC_TOP_BASE,    0x3284U,   4},
    {    GPIO_G23,    2,    PORT_IOMUXC_TOP_BASE,    0x3004U,   3},
    {    GPIO_G23,    3,    PORT_IOMUXC_TOP_BASE,    0x3104U,   2},
    {    GPIO_G23,    5,    PORT_IOMUXC_TOP_BASE,    0x3580U,   1},
    {    GPIO_G24,    3,    PORT_IOMUXC_TOP_BASE,    0x3114U,   2},
    {    GPIO_G24,    4,    PORT_IOMUXC_TOP_BASE,    0x32a0U,   1},
    {    GPIO_G24,    5,    PORT_IOMUXC_TOP_BASE,    0x3584U,   1},
    {    GPIO_G25,    3,    PORT_IOMUXC_TOP_BASE,    0x3120U,   2},
    {    GPIO_G25,    4,    PORT_IOMUXC_TOP_BASE,    0x32a8U,   1},
    {    GPIO_G25,    5,    PORT_IOMUXC_TOP_BASE,    0x3588U,   1},
    {    GPIO_G26,    3,    PORT_IOMUXC_TOP_BASE,    0x3130U,   2},
    {    GPIO_G26,    4,    PORT_IOMUXC_TOP_BASE,    0x32b0U,   1},
    {    GPIO_G26,    5,    PORT_IOMUXC_TOP_BASE,    0x358cU,   1},
    {    GPIO_G27,    3,    PORT_IOMUXC_TOP_BASE,    0x313cU,   2},
    {    GPIO_G27,    4,    PORT_IOMUXC_TOP_BASE,    0x3064U,   2},
    {    GPIO_G27,    5,    PORT_IOMUXC_TOP_BASE,    0x3594U,   1},
    {    GPIO_G27,    6,    PORT_IOMUXC_TOP_BASE,    0x3440U,   1},
    {    GPIO_G28,    1,    PORT_IOMUXC_TOP_BASE,    0x341cU,   3},
    {    GPIO_G28,    3,    PORT_IOMUXC_TOP_BASE,    0x314cU,   3},
    {    GPIO_G28,    4,    PORT_IOMUXC_TOP_BASE,    0x3318U,   1},
    {    GPIO_G28,    5,    PORT_IOMUXC_TOP_BASE,    0x33dcU,   2},
    {    GPIO_G29,    4,    PORT_IOMUXC_TOP_BASE,    0x3070U,   2},
    {    GPIO_G29,    5,    PORT_IOMUXC_TOP_BASE,    0x33e8U,   2},
    {    GPIO_G30,    1,    PORT_IOMUXC_TOP_BASE,    0x345cU,   3},
    {    GPIO_G30,    4,    PORT_IOMUXC_TOP_BASE,    0x331cU,   1},
    {    GPIO_G30,    5,    PORT_IOMUXC_TOP_BASE,    0x33f4U,   2},
    {    GPIO_G31,    1,    PORT_IOMUXC_TOP_BASE,    0x3438U,   3},
    {    GPIO_G31,    4,    PORT_IOMUXC_TOP_BASE,    0x3320U,   1},
    {    GPIO_G31,    5,    PORT_IOMUXC_TOP_BASE,    0x33fcU,   2},
    {     GPIO_F0,    1,    PORT_IOMUXC_TOP_BASE,    0x3398U,   1},
    {     GPIO_F1,    1,    PORT_IOMUXC_TOP_BASE,    0x33a8U,   1},
    {     GPIO_F2,    1,    PORT_IOMUXC_TOP_BASE,    0x33e0U,   1},
    {     GPIO_F3,    1,    PORT_IOMUXC_TOP_BASE,    0x33d4U,   1},
    {     GPIO_F4,    1,    PORT_IOMUXC_TOP_BASE,    0x33c8U,   1},
    {     GPIO_F5,    1,    PORT_IOMUXC_TOP_BASE,    0x33b8U,   1},
    {     GPIO_F6,    1,    PORT_IOMUXC_TOP_BASE,    0x33ecU,   1},
    {     GPIO_F8,    1,    PORT_IOMUXC_TOP_BASE,    0x33f8U,   1},
    {     GPIO_F9,    1,    PORT_IOMUXC_TOP_BASE,    0x3400U,   1},
    {    GPIO_F10,    1,    PORT_IOMUXC_TOP_BASE,    0x340cU,   1},
    {    GPIO_F11,    1,    PORT_IOMUXC_TOP_BASE,    0x3414U,   1},
    {    GPIO_F12,    1,    PORT_IOMUXC_TOP_BASE,    0x33a8U,   2},
    {    GPIO_F13,    1,    PORT_IOMUXC_TOP_BASE,    0x33ecU,   2},
    {   SYS_CTRL1,    3,    PORT_IOMUXC_RTC_BASE,    0x3000U,   0},
    {   SYS_GPIO2,    3,    PORT_IOMUXC_RTC_BASE,    0x3000U,   1},
    {   SYS_GPIO3,    3,    PORT_IOMUXC_RTC_BASE,    0x3000U,   2},
    {   SYS_GPIO5,    1,     PORT_IOMUXC_LP_BASE,    0x3000U,   0},
    {   SYS_GPIO7,    1,     PORT_IOMUXC_LP_BASE,    0x3004U,   0},
    {    JTAG_TDI,    3,     PORT_IOMUXC_LP_BASE,    0x3008U,   0},
    {    JTAG_TDO,    3,     PORT_IOMUXC_LP_BASE,    0x300cU,   0},
    {    GPIO_LA0,    3,     PORT_IOMUXC_LP_BASE,    0x3010U,   0},
    {    GPIO_LA0,    4,     PORT_IOMUXC_LP_BASE,    0x3014U,   0},
    {    GPIO_LA0,    5,     PORT_IOMUXC_LP_BASE,    0x3018U,   0},
    {    GPIO_LA0,    6,    PORT_IOMUXC_TOP_BASE,    0x3000U,   0},
    {    GPIO_LA1,    3,     PORT_IOMUXC_LP_BASE,    0x301cU,   0},
    {    GPIO_LA1,    4,     PORT_IOMUXC_LP_BASE,    0x3020U,   0},
    {    GPIO_LA1,    5,     PORT_IOMUXC_LP_BASE,    0x3024U,   0},
    {    GPIO_LA1,    6,    PORT_IOMUXC_TOP_BASE,    0x3004U,   0},
    {    GPIO_LA2,    3,     PORT_IOMUXC_LP_BASE,    0x3028U,   0},
    {    GPIO_LA2,    4,     PORT_IOMUXC_LP_BASE,    0x302cU,   0},
    {    GPIO_LA2,    5,     PORT_IOMUXC_LP_BASE,    0x3030U,   0},
    {    GPIO_LA2,    6,    PORT_IOMUXC_TOP_BASE,    0x3008U,   0},
    {    GPIO_LA3,    3,     PORT_IOMUXC_LP_BASE,    0x3034U,   0},
    {    GPIO_LA3,    4,     PORT_IOMUXC_LP_BASE,    0x3038U,   0},
    {    GPIO_LA3,    5,     PORT_IOMUXC_LP_BASE,    0x303cU,   0},
    {    GPIO_LA3,    6,    PORT_IOMUXC_TOP_BASE,    0x300cU,   0},
    {    GPIO_LA4,    1,     PORT_IOMUXC_LP_BASE,    0x3040U,   0},
    {    GPIO_LA4,    3,     PORT_IOMUXC_LP_BASE,    0x3044U,   0},
    {    GPIO_LA4,    4,     PORT_IOMUXC_LP_BASE,    0x3048U,   0},
    {    GPIO_LA4,    5,     PORT_IOMUXC_LP_BASE,    0x304cU,   0},
    {    GPIO_LA4,    6,    PORT_IOMUXC_TOP_BASE,    0x3010U,   0},
    {    GPIO_LA5,    1,     PORT_IOMUXC_LP_BASE,    0x3050U,   0},
    {    GPIO_LA5,    3,     PORT_IOMUXC_LP_BASE,    0x3054U,   0},
    {    GPIO_LA5,    5,     PORT_IOMUXC_LP_BASE,    0x3058U,   0},
    {    GPIO_LA5,    6,    PORT_IOMUXC_TOP_BASE,    0x3014U,   0},
    {    GPIO_LA6,    1,     PORT_IOMUXC_LP_BASE,    0x3008U,   1},
    {    GPIO_LA6,    3,     PORT_IOMUXC_LP_BASE,    0x305cU,   0},
    {    GPIO_LA6,    5,     PORT_IOMUXC_LP_BASE,    0x3060U,   0},
    {    GPIO_LA7,    1,     PORT_IOMUXC_LP_BASE,    0x300cU,   1},
    {    GPIO_LA7,    3,     PORT_IOMUXC_LP_BASE,    0x3064U,   0},
    {    GPIO_LA7,    4,     PORT_IOMUXC_LP_BASE,    0x3068U,   0},
    {    GPIO_LA7,    5,     PORT_IOMUXC_LP_BASE,    0x306cU,   0},
    {    GPIO_LA8,    1,     PORT_IOMUXC_LP_BASE,    0x3000U,   1},
    {    GPIO_LA8,    3,     PORT_IOMUXC_LP_BASE,    0x3070U,   0},
    {    GPIO_LA8,    4,     PORT_IOMUXC_LP_BASE,    0x3074U,   0},
    {    GPIO_LA8,    5,     PORT_IOMUXC_LP_BASE,    0x3078U,   0},
    {    GPIO_LA8,    6,    PORT_IOMUXC_TOP_BASE,    0x3018U,   0},
    {    GPIO_LA9,    3,     PORT_IOMUXC_LP_BASE,    0x307cU,   0},
    {    GPIO_LA9,    5,     PORT_IOMUXC_LP_BASE,    0x3080U,   0},
    {    GPIO_LA9,    6,    PORT_IOMUXC_TOP_BASE,    0x301cU,   0},
    {   GPIO_LA10,    1,     PORT_IOMUXC_LP_BASE,    0x3004U,   1},
    {   GPIO_LA10,    3,     PORT_IOMUXC_LP_BASE,    0x3084U,   0},
    {   GPIO_LA10,    5,     PORT_IOMUXC_LP_BASE,    0x3088U,   0},
    {   GPIO_LA10,    6,    PORT_IOMUXC_TOP_BASE,    0x3020U,   0},
    {   GPIO_LA11,    3,     PORT_IOMUXC_LP_BASE,    0x308cU,   0},
    {   GPIO_LA11,    5,     PORT_IOMUXC_LP_BASE,    0x3090U,   0},
    {   GPIO_LA11,    6,    PORT_IOMUXC_TOP_BASE,    0x3024U,   0},
    {   GPIO_LA12,    1,     PORT_IOMUXC_LP_BASE,    0x3094U,   0},
    {   GPIO_LA12,    3,     PORT_IOMUXC_LP_BASE,    0x3098U,   0},
    {   GPIO_LA12,    5,     PORT_IOMUXC_LP_BASE,    0x309cU,   0},
    {   GPIO_LA13,    1,     PORT_IOMUXC_LP_BASE,    0x30a0U,   0},
    {   GPIO_LA13,    3,     PORT_IOMUXC_LP_BASE,    0x30a4U,   0},
    {   GPIO_LA13,    5,     PORT_IOMUXC_LP_BASE,    0x30a8U,   0},
    {   GPIO_LA14,    1,     PORT_IOMUXC_LP_BASE,    0x30acU,   0},
    {   GPIO_LA14,    2,     PORT_IOMUXC_LP_BASE,    0x30b0U,   0},
    {   GPIO_LA14,    3,     PORT_IOMUXC_LP_BASE,    0x30b4U,   0},
    {   GPIO_LA14,    5,     PORT_IOMUXC_LP_BASE,    0x30b8U,   0},
    {   GPIO_LA14,    6,    PORT_IOMUXC_TOP_BASE,    0x3028U,   0},
    {   GPIO_LA15,    1,     PORT_IOMUXC_LP_BASE,    0x30bcU,   0},
    {   GPIO_LA15,    2,     PORT_IOMUXC_LP_BASE,    0x30c0U,   0},
    {   GPIO_LA15,    3,     PORT_IOMUXC_LP_BASE,    0x30c4U,   0},
    {   GPIO_LA15,    5,     PORT_IOMUXC_LP_BASE,    0x30c8U,   0},
    {   GPIO_LA15,    6,    PORT_IOMUXC_TOP_BASE,    0x302cU,   0},
    {   GPIO_LA16,    5,     PORT_IOMUXC_LP_BASE,    0x3038U,   1},
    {   GPIO_LA16,    6,     PORT_IOMUXC_LP_BASE,    0x30ccU,   0},
    {   GPIO_LA17,    5,     PORT_IOMUXC_LP_BASE,    0x3048U,   1},
    {   GPIO_LA24,    1,     PORT_IOMUXC_LP_BASE,    0x30d0U,   0},
    {   GPIO_LA24,    5,     PORT_IOMUXC_LP_BASE,    0x3014U,   1},
    {   GPIO_LA25,    1,     PORT_IOMUXC_LP_BASE,    0x30d4U,   0},
    {   GPIO_LA25,    5,     PORT_IOMUXC_LP_BASE,    0x3020U,   1},
    {   GPIO_LA26,    5,     PORT_IOMUXC_LP_BASE,    0x302cU,   1},
    {   GPIO_LA27,    5,     PORT_IOMUXC_LP_BASE,    0x30b0U,   1},
    {   GPIO_LA28,    5,     PORT_IOMUXC_LP_BASE,    0x30c0U,   1},
    {    GPIO_LD0,    1,     PORT_IOMUXC_LP_BASE,    0x3040U,   1},
    {    GPIO_LD0,    3,     PORT_IOMUXC_LP_BASE,    0x3010U,   1},
    {    GPIO_LD0,    6,    PORT_IOMUXC_TOP_BASE,    0x3030U,   0},
    {    GPIO_LD1,    1,     PORT_IOMUXC_LP_BASE,    0x3050U,   1},
    {    GPIO_LD1,    3,     PORT_IOMUXC_LP_BASE,    0x301cU,   1},
    {    GPIO_LD1,    6,    PORT_IOMUXC_TOP_BASE,    0x3034U,   0},
    {    GPIO_LD2,    1,     PORT_IOMUXC_LP_BASE,    0x3008U,   2},
    {    GPIO_LD2,    3,     PORT_IOMUXC_LP_BASE,    0x3028U,   1},
    {    GPIO_LD2,    6,    PORT_IOMUXC_TOP_BASE,    0x3038U,   0},
    {    GPIO_LD3,    1,     PORT_IOMUXC_LP_BASE,    0x300cU,   2},
    {    GPIO_LD3,    3,     PORT_IOMUXC_LP_BASE,    0x3034U,   1},
    {    GPIO_LD3,    6,    PORT_IOMUXC_TOP_BASE,    0x303cU,   0},
    {    GPIO_LD4,    1,     PORT_IOMUXC_LP_BASE,    0x3000U,   2},
    {    GPIO_LD4,    3,     PORT_IOMUXC_LP_BASE,    0x3044U,   1},
    {    GPIO_LD5,    2,     PORT_IOMUXC_LP_BASE,    0x30d8U,   0},
    {    GPIO_LD5,    3,     PORT_IOMUXC_LP_BASE,    0x3054U,   1},
    {    GPIO_LD6,    1,     PORT_IOMUXC_LP_BASE,    0x3004U,   2},
    {    GPIO_LD6,    3,     PORT_IOMUXC_LP_BASE,    0x305cU,   1},
    {    GPIO_LD7,    3,     PORT_IOMUXC_LP_BASE,    0x3064U,   1},
    {    GPIO_LD8,    1,     PORT_IOMUXC_LP_BASE,    0x3094U,   1},
    {    GPIO_LD8,    3,     PORT_IOMUXC_LP_BASE,    0x3070U,   1},
    {    GPIO_LD8,    6,    PORT_IOMUXC_TOP_BASE,    0x3040U,   0},
    {    GPIO_LD9,    1,     PORT_IOMUXC_LP_BASE,    0x30a0U,   1},
    {    GPIO_LD9,    3,     PORT_IOMUXC_LP_BASE,    0x307cU,   1},
    {    GPIO_LD9,    6,    PORT_IOMUXC_TOP_BASE,    0x3044U,   0},
    {   GPIO_LD10,    1,     PORT_IOMUXC_LP_BASE,    0x30acU,   1},
    {   GPIO_LD10,    3,     PORT_IOMUXC_LP_BASE,    0x3084U,   1},
    {   GPIO_LD10,    6,    PORT_IOMUXC_TOP_BASE,    0x3048U,   0},
    {   GPIO_LD11,    1,     PORT_IOMUXC_LP_BASE,    0x30bcU,   1},
    {   GPIO_LD11,    3,     PORT_IOMUXC_LP_BASE,    0x308cU,   1},
    {   GPIO_LD11,    6,    PORT_IOMUXC_TOP_BASE,    0x304cU,   0},
    {   GPIO_LD12,    2,     PORT_IOMUXC_LP_BASE,    0x30d0U,   1},
    {   GPIO_LD12,    3,     PORT_IOMUXC_LP_BASE,    0x3098U,   1},
    {   GPIO_LD12,    6,    PORT_IOMUXC_TOP_BASE,    0x3050U,   0},
    {   GPIO_LD13,    2,     PORT_IOMUXC_LP_BASE,    0x30d4U,   1},
    {   GPIO_LD13,    3,     PORT_IOMUXC_LP_BASE,    0x30a4U,   1},
    {   GPIO_LD13,    6,    PORT_IOMUXC_TOP_BASE,    0x3054U,   0},
    {   GPIO_LD14,    3,     PORT_IOMUXC_LP_BASE,    0x30b4U,   1},
    {   GPIO_LD14,    6,    PORT_IOMUXC_TOP_BASE,    0x3058U,   0},
    {   GPIO_LD15,    3,     PORT_IOMUXC_LP_BASE,    0x30c4U,   1},
    {   GPIO_LD15,    6,    PORT_IOMUXC_TOP_BASE,    0x305cU,   0},
    {   GPIO_LD16,    1,     PORT_IOMUXC_LP_BASE,    0x3040U,   2},
    {   GPIO_LD16,    2,     PORT_IOMUXC_LP_BASE,    0x30d0U,   2},
    {   GPIO_LD16,    3,     PORT_IOMUXC_LP_BASE,    0x3068U,   1},
    {   GPIO_LD16,    5,     PORT_IOMUXC_LP_BASE,    0x3058U,   1},
    {   GPIO_LD16,    6,    PORT_IOMUXC_TOP_BASE,    0x3000U,   1},
    {   GPIO_LD17,    1,     PORT_IOMUXC_LP_BASE,    0x3050U,   2},
    {   GPIO_LD17,    2,     PORT_IOMUXC_LP_BASE,    0x30d4U,   2},
    {   GPIO_LD17,    3,     PORT_IOMUXC_LP_BASE,    0x3074U,   1},
    {   GPIO_LD17,    5,     PORT_IOMUXC_LP_BASE,    0x3060U,   1},
    {   GPIO_LD17,    6,    PORT_IOMUXC_TOP_BASE,    0x3004U,   1},
    {   GPIO_LD18,    1,     PORT_IOMUXC_LP_BASE,    0x3008U,   3},
    {   GPIO_LD18,    5,     PORT_IOMUXC_LP_BASE,    0x306cU,   1},
    {   GPIO_LD18,    6,     PORT_IOMUXC_LP_BASE,    0x30ccU,   1},
    {   GPIO_LD19,    1,     PORT_IOMUXC_LP_BASE,    0x300cU,   3},
    {   GPIO_LD19,    5,     PORT_IOMUXC_LP_BASE,    0x3078U,   1},
    {   GPIO_LD20,    1,     PORT_IOMUXC_LP_BASE,    0x3000U,   3},
    {   GPIO_LD20,    5,     PORT_IOMUXC_LP_BASE,    0x3080U,   1},
    {   GPIO_LD20,    6,    PORT_IOMUXC_TOP_BASE,    0x3060U,   0},
    {   GPIO_LD21,    5,     PORT_IOMUXC_LP_BASE,    0x3088U,   1},
    {   GPIO_LD21,    6,    PORT_IOMUXC_TOP_BASE,    0x3064U,   0},
    {   GPIO_LD22,    1,     PORT_IOMUXC_LP_BASE,    0x3004U,   3},
    {   GPIO_LD22,    5,     PORT_IOMUXC_LP_BASE,    0x3090U,   1},
    {   GPIO_LD22,    6,    PORT_IOMUXC_TOP_BASE,    0x3068U,   0},
    {   GPIO_LD23,    5,     PORT_IOMUXC_LP_BASE,    0x309cU,   1},
    {   GPIO_LD23,    6,    PORT_IOMUXC_TOP_BASE,    0x306cU,   0},
    {   GPIO_LD24,    1,     PORT_IOMUXC_LP_BASE,    0x3094U,   2},
    {   GPIO_LD24,    5,     PORT_IOMUXC_LP_BASE,    0x30a8U,   1},
    {   GPIO_LD25,    1,     PORT_IOMUXC_LP_BASE,    0x30a0U,   2},
    {   GPIO_LD25,    5,     PORT_IOMUXC_LP_BASE,    0x30b8U,   1},
    {   GPIO_LD26,    1,     PORT_IOMUXC_LP_BASE,    0x30acU,   2},
    {   GPIO_LD26,    2,     PORT_IOMUXC_LP_BASE,    0x30d8U,   1},
    {   GPIO_LD26,    5,     PORT_IOMUXC_LP_BASE,    0x30c8U,   1},
    {   GPIO_LD27,    1,     PORT_IOMUXC_LP_BASE,    0x30bcU,   2},
    {   GPIO_LD27,    4,     PORT_IOMUXC_LP_BASE,    0x3014U,   2},
    {   GPIO_LD27,    5,     PORT_IOMUXC_LP_BASE,    0x3018U,   1},
    {   GPIO_LD28,    4,     PORT_IOMUXC_LP_BASE,    0x3020U,   2},
    {   GPIO_LD28,    5,     PORT_IOMUXC_LP_BASE,    0x3024U,   1},
    {   GPIO_LD28,    6,    PORT_IOMUXC_TOP_BASE,    0x3070U,   0},
    {   GPIO_LD29,    4,     PORT_IOMUXC_LP_BASE,    0x302cU,   2},
    {   GPIO_LD29,    5,     PORT_IOMUXC_LP_BASE,    0x3030U,   1},
    {   GPIO_LD29,    6,    PORT_IOMUXC_TOP_BASE,    0x3074U,   0},
    {   GPIO_LD30,    4,     PORT_IOMUXC_LP_BASE,    0x30b0U,   2},
    {   GPIO_LD30,    5,     PORT_IOMUXC_LP_BASE,    0x303cU,   1},
    {   GPIO_LD30,    6,    PORT_IOMUXC_TOP_BASE,    0x3078U,   0},
    {   GPIO_LD31,    4,     PORT_IOMUXC_LP_BASE,    0x30c0U,   2},
    {   GPIO_LD31,    5,     PORT_IOMUXC_LP_BASE,    0x304cU,   1},
    {   GPIO_LD31,    6,    PORT_IOMUXC_TOP_BASE,    0x307cU,   0},
};

/*
  IOMUXC_CPU:
    [0, 31] -> [GPIO_E0, GPIO_E31]
    [32, 63] -> [GPIO_M0, GPIO_M31]
  IOMUXC_LP:
    [0, 78] -> [SEM_FAULT0, GPIO_LD31]
  IOMUXC_MAIN_DOWN:
    [0, 47] -> [GPIO_H0, GPIO_G31]
  IOMUXC_MAIN_UP:
    [0, 31] -> [GPIO_X0, GPIO_Y15]
    [32, 63] -> [GPIO_S0, GPIO_S31]
    [64, 79] -> [GPIO_F0, GPIO_F15]
  IOMUXC_RTC:
    [0, 1] -> [SYS_MODE0, SYS_MODE1]
    [2, 2] -> [SYS_POR_B, SYS_POR_B]
    [3, 22] -> [SYS_BUTTON, SYS_GPIO16]
  IOMUXC_SF_TOP:
    [0, 95] -> [GPIO_K0, GPIO_C15]
*/
static const Port_PinMapType Port_PinctrlMaps[] =
{
    {GPIO_E0,    PORT_CPU_PIN_NUM,       0U,  PORT_IOMUXC_CPU_BASE},
    {GPIO_M0,    PORT_CPU_PIN_NUM2,      32U, PORT_IOMUXC_CPU_BASE},
    {SEM_FAULT0, PORT_LP_PIN_NUM,        0U,  PORT_IOMUXC_LP_BASE},
    {GPIO_H0,    PORT_MAIN_DOWN_PIN_NUM, 0U,  PORT_IOMUXC_MAIN_DOWN_BASE},
    {GPIO_X0,    PORT_MAIN_UP_PIN_NUM,   0U,  PORT_IOMUXC_MAIN_UP_BASE},
    {GPIO_S0,    PORT_MAIN_UP_PIN_NUM2,  32U, PORT_IOMUXC_MAIN_UP_BASE},
    {GPIO_F0,    PORT_MAIN_UP_PIN_NUM3,  64U, PORT_IOMUXC_MAIN_UP_BASE},
    {SYS_MODE0,  PORT_RTC_PIN_NUM,       0U,  PORT_IOMUXC_RTC_BASE},
    {SYS_POR_B,  PORT_RTC_PIN_NUM2,      2U,  PORT_IOMUXC_RTC_BASE},
    {SYS_BUTTON, PORT_RTC_PIN_NUM3,      3U,  PORT_IOMUXC_RTC_BASE},
    {GPIO_K0,    PORT_TOP_PIN_NUM,       0U,  PORT_IOMUXC_TOP_BASE},
};

/*
  GPIO_SF1:
    [0, 191] -> [GPIO_K0, GPIO_M31]

  GPIO_SF2:
    [0, 95] -> [GPIO_X0, GPIO_F15]

  GPIO_LP:
    [0, 102] -> [SYS_MODE0, GPIO_LD31]
*/
static const Port_PinMapType Port_GpioMaps[] =
{
    {GPIO_K0,   192U, 0U, PORT_GPIO_SF1_BASE},
    {GPIO_X0,   96U,  0U, PORT_GPIO_SF2_BASE},
    {SYS_MODE0, 103U, 0U, PORT_GPIO_LP_BASE},
};

#define PORT_STOP_SEC_CONST_UNSPECIFIED
#include "Port_MemMap.h"


#ifdef __cplusplus
}
#endif
/* End of file */
#endif /* PORT_PINMAP_H */
